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Battery performance optimizer circuit / rush current supplier with ultra slow quiescent current and high efficeincy

Other Parts Discussed in Thread: BQ25505, TPS62770


I am working on a project for demanding of above circuit with below requirements:

1. Circuit main power source is from a primary battery (3.6V), optimized current drawn from battery is < 50mA for maximizing of battery life.

2. A super capacitor(s) shall be built to absorb rush current from loading, so as to maintain the current drawn from primary battery nearly constant for optimized life time of the battery. Peak current could be 300mA lasting for seconds and the normal current consumption could be <20uA.

3. The quiescent current of the circuit shall be as low as possible, better <1uA

4. The efficiency of the the circuit shall be > 80%, normally ~90% or above.

We used LTC3225 for this design previously, but unfortunately the quiescent current exceeds our requirement.

Does TI have similar PMIC chips to meet above requirements?

We studied BQ25505 for this design, just one thing confused me. It is the VC_IN supply always plays the highest priority to supply power to loadings, whereby this current is limited at 230mA (peak) and 100mA(average). However, our design target is lower down the current supplied from VC_IN (~50mA adjustable), is there any way to do that? or you can recommend another IC chip to replace it?

Another question is for TPS62770, whereby it has a LOAD output switched from V01_out. Does this LOAD output voltage level always equals (or just a little bit lower than it because the voltage drop over the MOSFET switch) to V01_out when the CTRL is high? In your DS, it confuses me since the LOAD output is always put as 1.8V output.

Looking forward to your reply.