Hi,
When I test BQ24610 circuit, I found a voltage fall back when high-side Vgs is lifting, is there a way to avoid? ps: hide-side mos: NTMFS4941NT1G, low-side mos: NTMFS4935NT1G
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Hi,
When I test BQ24610 circuit, I found a voltage fall back when high-side Vgs is lifting, is there a way to avoid? ps: hide-side mos: NTMFS4941NT1G, low-side mos: NTMFS4935NT1G
For best practice, it is better to have all power components on the same layer and use the ground layer as shield, especially all the switching elements.
From your waveform earlier, it looks like the voltage spike on VGS is highly likely caused by the parasitic inductance. It is highly important that you have your high frequency switching loop as small as possible. Below is an example.