TPS54824: SYNC clock

K.Hamamoto

Part Number: TPS54824

Our customer are concerned about the edge of SYNC pin clock. On the datasheet, it is mentioned as below,

We understand the sync clock is synchronized to the falling edge.

However is the rising edge of sync clock affect any internal operation? (Is it not only synchronized operation but also affect to any other operation?.)

Regards,

Koji Hamamoto

over 7 years ago

0 JohnTucker over 7 years ago

TI__Guru**** 191445 points

Koji,
Please make sure that you follow the recommendations regarding amplitude and duty cycle. As long as teh rising and falling edges are not too close together, there are no issues with the rising edge.

0 Anthony F over 7 years ago in reply to JohnTucker

TI__Mastermind 35165 points

If possible, I do also recommend keeping the rising edge of the CLK away from the falling edge of the SW node. If these line up, you may see increased jitter due to the external clock edge coupling with the control signals. For example, if you have a 20% duty cycle application I would try to keep the CLK duty cycle <80% plus some margin. This way the HS FET always turns off before the CLK rising edge.

0 K.Hamamoto over 7 years ago in reply to Anthony F

Guru 12155 points

Hi John, Anthony

Thank you for your kindness support.

Regards,
Koji Hamamoto

Power management

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TPS54824: SYNC clock