TPS659037: About Power sequence

Gk 110

Expert 2440 points

Part Number: TPS659037
Other Parts Discussed in Thread: AM5726, TPS65917-Q1

To whom it may concern,

I have question about power sequence of TPS6590378.

(Customer Conditions)

　1, Customer system is suddenly powered.

　　Also, when the system is turned off, the power supply is instantly interrupted.

　2, Customer would like to design a system that automatically starts up and shuts down, when there is occurred above conditions.

(Question)

- For power up;

When POWERHOLD pin is connected to LDOVRTC(pull-up), is "ON Request" executed successfully?

- For power down;

If POWERHOLD pin is pulled up, is the shutdown executed normally?

Could you please confirm the attached file about the detail?

After you check the attached file, could you please point out if there is a problem part about the attached file?

Best regards,

Gk110

TPS6590378　Diagram.pdf

over 7 years ago

0 Gordon Varney over 7 years ago

TI__Genius 9380 points

GK110,
I am forwarding your question to a product specialist. Thank you for using E2E.

0 Karl Wallinger over 7 years ago

TI__Genius 16410 points

Hello,

> When POWERHOLD pin is connected to LDOVRTC(pull-up), is "ON Request" executed successfully?
Yes, if POWERHOLD is connected to LDOVRTC, the device will start up immediately when VCC1 > VSYS_HI (3.1V).

> If POWERHOLD pin is pulled up, is the shutdown executed normally?
The device will shut down, but will not follow the power-down sequence. The reason is that when VCC1 < VSYS_LO (2.75V), the device shuts off all outputs at the same time due to VCC1 undervoltage. In this case, you will not meet the power-down sequence of the processor, which could cause long-term issues.

I would suggest using the PGOOD of the DCDC converter supplying the PMIC, or a supervisor on the 24V rail itself, to shut off the PMIC when power is removed. This also will enable the PMIC when the PMIC is first supplied. You can see two examples in this blog post:
e2e.ti.com/.../how-to-meet-power-sequencing-requirements-with-a-pmic

Please let me know if you have any questions about this.

Regards,
Karl

0 Gk 110 over 7 years ago in reply to Karl Wallinger

Expert 2440 points

Hi Karl-san

Thank you for your kindly reply.
I confirmed E2E that you introduced.
e2e.ti.com/.../how-to-meet-power-sequencing-requirements-with-a-pmic

I understood that VCC of TPS659037 needs to be kept at 2.75 V or more for more than 1 ms.

I refered the following equation.
C=I*⊿t / (Vcc-Vmin) --- (1)
If Vcc is 5V and I=3A,the capacitor needs 1.3mF.

Is this right?

They can't use big capacitor in this project.
Is there other good way to resolve it?

Best regard

Gk110

0 Karl Wallinger over 7 years ago in reply to Gk 110

TI__Genius 16410 points

Hi GK,

If the system has 5V supply and 3A current on the 5V, they will need 1.3mF of capacitance to hold it up for 1ms - actually, the power-down sequence for TPS6590378 is 1.6ms, so the actual capacitance per the calculation is 2mF. This is the worst-case number. The only way to support this is to increase capacitance or decrease the load current.

In reality, after the POWERHOLD signal is set low to turn off the PMIC, the power-down sequence starts executing, and the load current should start decreasing. Within 100us, RESET_OUT, LDO1, LDO2, LDOUSB, and REGEN1 (VDDSHVx) will all be disabled. So this is probably the current you should use when calculating the discharge time of the input supply.

After another 500us, all the CORE supplies (SMPS12, SMPS3, SMPS45, SMPS6, and LDO9) are all disabled. This will reduce the current further.

Then 1000us after that, the remaining rails are disabled. At this point, the voltage does not matter, since all outputs are off.

So you could calculate the voltage at the inputs in 3 steps, assuming POWERHOLD goes low at t=0:

From t=0us to t=100us, you will have your full load current
From t=100us to t=600us, you will have lower load current while processor is in reset, and LDO1/2/USB and VDDSHVx are disabled
From t=600us to t=1600us, you will have lower load current while CORE rails are disabled

Based on this current profile, you should be able to determine the minimum capacitance to keep VCC > 2.75V at t=1600us.

Or, if you still have too much load current, you would need to look at reducing the load current. For example, when the system knows that the power is dropping, the processor may be able to scale back frequency, or disable I/Os, etc.

Regards,
Karl

0 Gk 110 over 7 years ago in reply to Karl Wallinger

Expert 2440 points

Hello Karl-san

I understand your description.

However, I have some additional question.

Q1 : Could you please teach that is predicted current at below each situation?

a, From t=0us to t=100us, you will have your full load current

b, From t=100us to t=600us, you will have lower load current while processor is in reset, and LDO1/2/USB and VDDSHVx are disabled

c, From t=600us to t=1600us, you will have lower load current while CORE rails are disabled

Are there general indicators?

Q2 : If the customer designs as follows, how should they consider about the capacitor at shutdown?

In this design, it is supplied 3.3V and 5V to PMIC.

Reference design is "Figure 1. Processor Connection With TPS6590378ZWSR" in user's guide(SLIU011E).

Q3 : What is the shortest time until we cannot be access the device (NAND FROM) connected to GPMC after putting the POWER HOLD signal into the PMIC?

Q4 : When power supply is removed unexpectedly, is there how to forcibly lower power consumption of AM5726?

Our customer would like to know the way to reduce the capacitor value.

For example, a method of forcibly lowering the operating frequency of AM 5726, etc.

Best regards,

Gk110

0 Karl Wallinger over 7 years ago in reply to Gk 110

TI__Genius 16410 points

Hello GK,

Q1 : Could you please teach that is predicted current at below each situation?

[Karl] This will depend on the end application. I believe there is a tool to estimate power consumption based on processor usage, but you may need to get that from the Sitara team.

Q2 : If the customer designs as follows, how should they consider about the capacitor at shutdown?

[Karl] The main concern is the VCC1 supply. This needs to be held above 2.75V until the last step in the sequence. So this rail should probably have more capacitance, as it will also have more load current through the SMPS.

Q3 : What is the shortest time until we cannot be access the device (NAND FROM) connected to GPMC after putting the POWER HOLD signal into the PMIC?

[Karl] Do you mean after POWERHOLD goes low? After POWERHOLD goes low, the PMIC immediately cannot be accessed by I2C. Any I2C communication has to happen before POWERHOLD is set low.

Q4 : When power supply is removed unexpectedly, is there how to forcibly lower power consumption of AM5726?

[Karl] This may be a better question for the Sitara team, but I think the most likely would be to decrease the processor clock frequencies, and decrease I/O communication.

Regards,
Karl

0 Shinichi Inoue over 7 years ago in reply to Karl Wallinger

Guru 21701 points

Hi Karl,

I'm a coleague of GK.

At this time I ask you about the customer's question instead of him.

I would be grateful if you could advise.

---
There are only two types of input pins that can generate an OFF request of the power-down sequence (OFF2ACT) of the processor: PWRON pin (long press) or PWRDOWN pin (level).

Please tell me if you have any.

---

I appreciate your great help.

Best regards,
Shinichi

0 Karl Wallinger over 7 years ago in reply to Shinichi Inoue

TI__Genius 16410 points

Hello Shinichi,

There are more than 2 OFF requests - these are all listed in section 5.3.2.2 of the datasheet:
www.ti.com/.../detailed-description

If you're specifically asking about pins, you can also use POWERHOLD/GPIO_5 (low=off) and RESET_IN/GPIO_1 (low=off) to generate an OFF request. You are right that PWRON is the only one which will turn off due to a long press.

Note that POWERHOLD, RESET_IN, and PWRDOWN are all OTP selectable, and may be selected by default depending on the exact OTP you are using.

Regards,
Karl

0 Shinichi Inoue over 7 years ago in reply to Karl Wallinger

Guru 21701 points

Hi Karl,

Thank you for your reply.

It may be confuse, I'd like to confirm.

---

(1) The URL you attached is about TPS65917-Q1, is your answer the same as TPS6590378.

(2) The customer'd like to know,which pins and registers can generate OFF2ACT just in case.

He think PWRON and PWRDOWN, is it correct?

He'd like to know whether there are other way.

---

I appreciate your great help.

Best regards,

Shinichi

0 Karl Wallinger over 7 years ago in reply to Shinichi Inoue

TI__Genius 16410 points

Hi Shinichi,

That was my mistake, I'm sorry for the confusion. But the TPS659037 has the same table, with almost the same off requests. Here is the correct link:
www.ti.com/.../off-requests-slis1655002

Let me also confirm, you mentioned the OFF2ACT sequence, but you were previously discussing the power-down sequence. Just to be clear, the power-up sequence is the OFF2ACT sequence, and the power-down sequence is the ACT2OFF sequence.

In TPS659037, RESET_IN can generate a power-off request, and POWERHOLD/GPIO_7 can also generate a power-off request. The PWRON long press key and PWRDOWN can also generate OFF request as you mentioned. The full list of OFF requests is in table 5-10, as linked above.

Regards,
Karl

0 Shinichi Inoue over 7 years ago in reply to Karl Wallinger

Guru 21701 points

Hi Larl,

Thank you for your reply.

I understand the relationship between OFF2ACT and ACT2OFF. The customer may also confuse.

There are 4 pins of power-off request,RESET_IN, POWERHOLD/GPIO, PWRON long pressing and PWRDOWN.

I'll share these information with the customer.

I appreciate your great help and cooperation.

Best regards,
Shinichi

0 Shinichi Inoue over 7 years ago in reply to Karl Wallinger

Guru 21701 points

Power management

Power management forum

TPS659037: About Power sequence