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LM3940: PCB layout and capacitor selection

Part Number: LM3940

Attached is a picture of my current 4-layer PCB layout surrounding the LM3940. Via holes are 12mil. On the input line there is a 0.47uF MLCC. On the output line there is a 47uF (!6.3V) tantalum capacitor. Are the thermal relief connections problematic? Assuming that the ground plane is well "stitched" (it should be stitched with the internal ground plane right?), is the grounding for the regulator OK? What about the 5V in and 3.3V out? To me it looks kind of hackish (which I guess it is).

In front of the LM3940 there is a DC/DC regulator that has an output ripple Pk-Pk of 27mV. The LM3940 DS states that the input voltage has to be well regulated. Is this well-regulated? If not, what capacitors would you suggest adding to the input. The DS only specifies low ESR for these capacitors, not the capacitance.

  • Hi Johan,

    The GND plane is the primary heatsink for any LDO.  As such we do not recommend thermal relief on the GND pin or more importantly the GND tab.  More metal at these connections allows for more heat to be pulled from the LDO into the GND plane lowering the junction temperature of the LDO.

    The junction temperature of your LDO depends on your load, ambient temperature, and more.  We can estimate the junction temperature using RθJA from the Thermal information table in the datasheet.

    Tj = Pd x RθJA + Ta

    Pd = (Vin - Vout) x Iout

    Keep in mind that the maximum recommended junction temperature for LM3940 is 125 C.

    The statement about the input needing to be well regulated is meant to generate thought about the transients expected in the application.  The better regulated the input to the LDO, the better regulated the output will be as well.  A transient on the input will be reduced by the PSRR of the LDO; however, you will still see a transient on the output.

    Very Respectfully,


  • Hi Ryan,

    Thank you very much for the feedback on the layout, I've since removed the thermal reliefs (let's hope this doesn't make soldering much harder).

  • Hi Johan,

    as Ryan already mentioned, it's not wise to isolate the ground pins of LM3940 with heat traps from the ground plane. You lose a huge amount of cooling when doing this! The omitting of heat traps is no problem for automatic soldering (vapor phase, etc.) But for hand soldering it is. One remedy is to preheat the PCB to about 100°C with a fan and then solder with the iron. Do it carefully! Use the suggested layout of datasheet (figure 15). If this doesn't work for you, you should switch to a regulator with heat sink.

    Like many other LDOs the LM3940 doesn't provide good ripple rejection of input voltage. So, feeding the input with a Switcher isn't a good idea, unless you provide some fltering. You could take a pi-filter with two 47µF/25V aluminium electrolytics, one at the output of switcher and one at the input of LM3940. Parallel each of them with a 470n/X7R/0805 and put between the both arrangements a 10µH choke. Put also a resistor in series to the choke to dampen the LC-resonance. R should fullfill the follwowing relationship: R>=SQRT(2L/C)= 0.65R. The LM3940 should work stable with this 47µF input capacitance. If not increase to 100µF. But take care, some switchers have a maximum load capacitance specification. Don't violate this.

    One last hint: Keep an eye on the ESR requirement of output cap. Test the circuit at various ambient temperatures and load currents!

  • Hi Kai,

    Thank you so much for the detailed response. The switcher (OKL-T/1-W12P-C) is operating at 800kHz (peculiarly the output ripple in the performance charts in the data sheet seem to have a frequency of ~600kHz), which unfortunately seem to resonate(?) with the LDO, as it can only maintain a ripple rejection of ~26dB at this frequency. But I have to admit, to me, this still looks acceptable:

    [Switcher] 27mV peak-to-peak* @ 800kHz -> [LDO, 26dB rejection] -> 1.35mV peak-to-peak @ 800kHz(?)

    The microcontroller I'm using can handle up to 100mV peak-to-peak ripple at its input, so I would assume I'm well within specs? I realize that this might deviate a lot from reality, but I would assume it is a slight indicator that the set-up should be adequate?

    * Data sheet performance charts are based on 10µF output capacitor. I will be using a 22µF capacitor, as well as the input capacitor on the LDO. The data sheet also recommends to use a minimum of capacitance on the output to avoid instability, thus I'm a bit skeptic using an additional pi-network.

  • Hi Johan,

    yes, the switcher's noise seems to be tolerable. But keep an eye on it...