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LP3965: Layout guidelines for the LP3965EMP-ADJ/NOPB device

prachi p
Intellectual 300 points
Part Number: LP3965
Other Parts Discussed in Thread: LP3962

Hi,

Where can I find the layout guidelines or an example layout for the LP3965EMP-ADJ/NOPB LDO?

Regards,

Prachi

  • 0
    TI__Guru 55940 points
    Hi Prachi,

    We have layout guidelines in the PCB LAYOUT section on page 11 of the current datasheet revision (SNVS066H). Further information is available in other sections to provide additional information for a specific topic such as the capacitor location or thermal considerations.

    In general for any LDO we recommend that the input and output capacitors be placed as close as possible to their respective pin. It is recommended that the capacitors be connected without vias to both in/out and GND. As the GND plane is the primary heatsink for an LDO it is recommended to have as large of a GND plane as possible in your application.

    Very Respectfully,
    Ryan
  • 0
    Guru 140200 points
    Hi Prachi,

    in the datasheet I found this here:

    "It should be noted that stability problems have been seen in applications where "vias" to an internal ground plane
    were used at the ground points of the LP3962/5 IC and the input and output capacitors. This was caused by
    varying ground potentials at these nodes resulting from current flowing through the ground plane. Using a single
    point ground technique for the regulator and it's capacitors fixed the problem."

    Hhm, I wouldn't take this regulator...

    Kai