CCS/UCD3138064: Does it have the The internal block diagram about I2C-EEPROM ?

I'll assume you're talking about using the I2C in master mode, since we just discussed it that way.

In master mode, reading from I2CRXBUF is what triggers the hardware to read the next byte. 

So after you get a DATA_READY high, indicating that data has been read, the hardware will stretch the clock until you read from I2CRXBUF, or until it hits the 35 millisecond timeout, whichever comes first. 

Just in general, the I2C/PMBus interface logic can't be shown very well in a block diagram.  The requirement and the design are pretty complicated.