UCD3138064: Question about:OVERSAMPLE and the delay of the controller

user4768560

Part Number: UCD3138064

i want to design a buck converter with 200kHz switching frequency . i hope the bandwidth of close loop get up to 30KHz, i konw there is a pure lag :e^(-j*w*Tdpwm), so i think i can use oversample X8,but there is useless.

So do you know how to use the oversample? Whats wrong??? the pure lag is fixed by the switching frequecy? how can operate the system with no pure lag in my foucs bandwidth？

With best regards

over 7 years ago

0 Yitzhak Bolurian over 7 years ago

TI__Mastermind 18370 points

The delay of the PID filter from the time the EADC samples till it is ready for duty cycle update at DPWM side is about 500 nS.

Where did you place your sample trigger? You should have it at 4500 ns(500 nS before the end of period).

This way the EADC will sample at each 4500/8 = 562.5 nS interval, which is spread enough for the filter to be able to process and propagate each sample.

But, since you have EVENT_UP_SEL set to 1, the duty cycle will only update once in a switching cycle.

What is your topology? In most topologies we do recommend to set the EVENT_UP_SEL to 1.

Hope this helps.