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TPS24710: Internal Behavior When Pulling EN Pin to Low

Sadanori Kato
Guru 36540 points
Part Number: TPS24710

Hi,

There is mentioned on page 14 of TPS24710 data sheet that the GATE pin is discharged by a internal 20kΩ resistor to GND if the chip die temperature exceeds the OTSD rising threshold.
So, is the GATE pin discharged by a internal 20kΩ resistor as well when pulling the EN pin to low ?
If yes, is it possible to apply a bias voltage(1V ~ 1.5V) to the GATE pin with external divider resistors(the low impedance) when pulling the EN pin to low ?

Best regards,
Kato

  • 0
    TI__Expert 5940 points
    Kato,

    Same section 8.3.1.4 in the DS "Gate" describes the 11mA current sink pulling the gate low when Enable is low. I don't recommend anything be tied to the gate other than perhaps a very small SS dv_dt cap to supplement Crss of the FET to slow turn on if you don't want Plim power up. Remember the timer is active during start so the cap needs to be very small. So I would not recommend any other external circuit be tied to gate.

    Brian
  • 0 in reply to Brian Daugherty
    Guru 36540 points

    Hi Brian-san,

    Thank you for your response.

    I understood and will contact you if I get additional questions from our customer.

    Best regards,
    Kato