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LMG5200: Minimal off time for upper FET to recharge the bootstrap C

beat Ronner
Intellectual 405 points
Part Number: LMG5200
Other Parts Discussed in Thread: LMG1210

Hello TI

What is the minimal off-time for the upper FET needed to recharge the bootstrap-C?

To calculate this, I would need a inner R of the charge path, so I can calculate a RC-time-constant of the charge-circuit. I will be using a 0.1 uF bootstrap C as recommended in the manual.

Regards

Beat Ronner

  • 0
    TI__Expert 3225 points
    Hi Beat,

    Thanks for your interest. Please refer to the dynamic resistance in the bootstrap diode part in our datasheet for this resistance information.

    Thanks and regards,
    Lixing
  • 0 in reply to Lixing Fu
    Intellectual 405 points
    Hello Lixing

    Thanks for your reply - and yes, this gives the Information I was looking for.
    But the result troubles me a bit:

    I tried to calculate how close to duty-cycle 1 I can go with the upper FET. So I calculated
    - the charge used for my maximum on-time (2 us) according to your formula (2)
    - the current needed to replace this charge in 100 ns (Modulation index 0.9) and 50 ns (Modulation index 0.95)
    - the voltage drop over the bootstrap diode at above currents

    This gives me how low the voltage of the bootstrap-C would need to drop to draw the needed recharge-current. So I compared this voltage with the lowest voltage where the upper FET still works properly ( I took the HB undervoltage rising edge threshold V_HBR for this.)

    What I found:
    With the typical values of Diode Forward voltage, Diode R and V_HBR, all is fine.
    But with the worst-case values of all These Parameters: V_HBR,max=3.9V, VDH=1.0V I am already almost at the undervoltage trip Level (5V supply voltage minus 1V Forward drop means the boostrap voltage would be at only 4.0 V already at almost 0 current, with a trip threshold at 3.9 V).

    What is your experience here? How Close can I go to duty cycle 1.0 for the upper FET?
    (My application is a DC-buck converter application with fPWM=500 kHz)

    Best regards
    Beat
  • 0 in reply to beat Ronner
    TI__Expert 3225 points

    Hello Beat,

    1. There is a hysteresis of 200mV for the UVLO as stated in the datasheet for falling edge. So I would not worry that much on the voltage drop. Also the 1V VDH and 3.9V (Typicall value 3.2V),  V_HBR max are both max. condition, with 100mA of current. I doubt if you will have such a current when you are using GaN. But overall, this is extreme case and we have not observed issues with LMG5200 switching. 

    2. For the max. duty cycle, you can use the formula (2) that is in the datasheet to calculate. You can also use a smaller bootstrap cap to reduce your RC constant for charging up the cap.

    If you are really going to extreme duty cycle, another suggestion is to have a "burst-mode" like design, in which you have close to 1 duty cycle at 500kHz but turn on the low side FET longer every certain cycles. This can help you maintain your bootstrap voltage. 

    Thanks and regards,

    Lixing

  • 0 in reply to Lixing Fu
    Intellectual 405 points
    Hello Lixing

    To your point 1.:
    How is the hysteresis to be understood: Does undervoltage protection
    - become active at (typ. 3.2 / max 3.9 V), and is reset at (typ. 3.2 / max 3.9 V)+ 200 mV,
    - become active at (typ. 3.2 / max 3.9 V) -200mV, and reset at (typ. 3.2 / max 3.9 V)?

    You say I’ll never get 100 mA. If I calculated right, I do:
    If I want a modulation index of 0.95 for a H-bridge with 500 kHz, this means 50 ns off, 1.95 us on. So I would have to replace roughly 6.1 nC in 50ns, which means an average current of 122 mA.
    The 122 mA will cause a worst-case voltage drop of 1.34 V over the bootstrap-diode, so with a 5 V supply voltage, I’m down at 3.66 V. If the undervoltage protection reacts at 3.9 V, I could not operate the device like this.
    (I could not even do a modulation index of 90%)

    Yes, you are right, I did combine worst-cases. But I will have roughly 1000 converter boards with each 2 of LMG5200, i.e. roughly 2000 of your devices. So if there is no systematic exclusion of a combination of the worst cases (e.g. trip level is only high at very high temperatures, but then diode uF and R are small), I would guess that statistic says I will also have some samples with this worst-case combination.
    What is your experience here?
    Anyway, it's mainly the high deviation in the undervoltage threshold value that causes the trouble. Is this deviation really that high?

    To your point 2:
    If I understand it right, decreasing the C would not help. The time constant would get smaller, but the dV in one on-cycle would also get higher. But the fact that I have to replace a given charge in a given time does not depend on the C.

    To your point 3:
    Yes, good point. Thanks for that

    Would it evlt. be possible to connect a potential-separated voltage-supply chip to the HS-HB pins to supply the upper driver stage not via bootstrap-C, but externally? Maybe somebody has even tried out this? Would be great if there is experience around.

    Regards & thanks a lot for your advice
    Beat
  • 0 in reply to beat Ronner
    TI__Prodigy 645 points

    Hi Beat,

      Just to clarify, the rising-edge max is 3.9V and falling-edge max is 0.2V typ below it. So generally it should still work down to 3.7V if it started higher than that at some point.

    Your bootstrap current calculation looks right, however your diode drop calculation is wrong. The 1V diode drop specified on the datasheet is measured at 100 mA as is the dynamic resistance, so you have 22 mA more than that. So you have 0.022*2.8=0.0616V more than the 1V on the datasheet or 1.0616V total drop on the diode. So currently you are down to 3.94V worst case.

    Also, do you have a minimum load on your converter? What is your dead time? The minimum load will help push the switch node down when the low-side fet is on (for a buck-type converter only) and add to bootstrap voltage (on the order of IL*Rdson). The conduction during the dead times will help as well but is harder to quantify.

    If this does not work (maybe due to supply variation or some such) you can carefully put an external diode (or even a schottky) as a bootstrap diode which can help the bootstrap voltage stay up, however then you are responsible for making sure the high-side bootstrap voltage is not overcharged. Putting an external bootstrap diode will defeat the internal bootstrap voltage clamping mechanism. Alternatively, the LMG1210 driver + external FETs has a more flexible bootstrap configuration which has less severe constraints.

    Regards,

    Nathan

  • 0 in reply to Nathan Schemm
    Intellectual 405 points
    Good morning Nathan

    Thanks for your clarification on the diode forward voltage.
    So the way it should be calculated is
    uf=uf@100mA + (i-100mA)*Rdyn, correct?

    The offset of 100 mA in Rdyn*i helps of course.

    I did probably not get the point with the external diode. Do you recommend to do this because then, I can take a diode with less voltage drop?

    How about connecting a potential separated 5V power supply to the HB-HS pins? Do you know whether anybody tried?
    Of course this could be problematic because of the parasitic C this would add to the HS node.

    Regards & thanks a lot
    Beat
  • 0 in reply to beat Ronner
    TI__Prodigy 645 points

    Hi Beat,

    Yes, you are correct on your diode drop calculation.

    If you use an external bootstrap diode, you can use a schottky with a lower forward drop and therefore relax your constraints. However, the HB-HS clamp in the LMG5200 works by disabling the bootstrap diode when the bootstrap voltage is getting to high. An external bootstrap cannot be disabled, so you are removing the internal HB-HS voltage clamp by putting an external bootstrap diode. Therefore you have to supply your own clamp in that case (maybe with a parallel 5V zener or some such).

    Applying a 5V potential between the HB-HS pins is a great way of powering the high-side, however that generally involves producing an isolated high-side supply with low capacitance to ground. This is usually bigger and more expensive than other methods so is rarely done unless absolutely required, (for example if you want to be able to turn the high-side on with 100% duty cycle then this is required).

    Thanks,

    Nathan

  • 0 in reply to Nathan Schemm
    Intellectual 405 points
    Thanks a lot, Nathan

    Happy Easter