UCC28780: Design documents

Hello Gerrit,

Thank you for your interest in the UCC28780 ACF controller. I’m sorry that the current datasheet is unclear in places and we will work to improve it. I agree that it is a very complex device with its many operating modes to keep efficiency high across line and load.

Regarding Section 8.2.2.2.1 in the datasheet: ΔVclamp is the excess voltage that may appear across the clamp capacitor above the normal reflected voltage. Normally, Vclamp ≈ Vreflected with some ripple on it, but under certain conditions, the cap voltage can be driven higher temporarily. Without yet knowing what the turns ratio or the reflected voltage are, so we will have to assign an allowable value to ΔVclamp by an educated guess. I recommend to set ΔVclamp to 20~30V as a first estimate. This can be enforced by adding a TVS across Cclamp with break-over value = Vclamp + ΔVclamp.

Similarly, ΔVspike is estimated from experience based on previous flyback designs where the leakage inductance spike across the output rectifier is usually limited by an R-C snubber. I recommend to set ΔVspike = 20~30V as an initial estimate.

Regarding Kres, I agree that sentence is not clear. It was intended to mean “Use Kres = 5~6% as an initial estimate.” Or rather, Kres = 0.05 to 0.06 in equation 23. Since the datasheet was written we have found that the resonant portion of the switching period (the Kres) is about 5% in lower frequency designs (150-300kHz), but is more like 10~12% in higher frequency designs (400-800kHz).

Fsw(min) is the lowest switching frequency at which the designer wishes to operate at maximum output power and minimum bulk voltage. Choosing this value is also a matter of experience involving size and efficiency tradeoffs. Silicon MOSFET power stages operate at lower frequencies than GaN MOSFET power stages.

Because there are more unknown variables than independent equations, it may require some iteration through the calculations to arrive at optimal values.

Regarding the Mathcad issues:
1. For cases where Nps(min) > Nps(max), I agree that a test should flag this condition. In such cases, one or more of the constituent variables needs to be adjusted such that min < max. For example, if you have a very high max bulk voltage, then either the output rectifier voltage rating or the primary mosfet rating needs to be increased (or both), to make the inequality work correctly.
I recommend against trying to choose a turns ratio from these numbers when min > max.
2. It is true that the calculation for kZmax is valid only when VBULK < VRfl. It is wrong when VBULK > Vrfl. It is a good idea to clarify this point in a future Mathcad upgrade.
3. To determine the rating of the clamp capacitor(s), the reflected voltage needs to be calculated first from the output voltage and selected Nps turns ratio. The voltage rating for Cclamp should be sufficient for the highest reflected voltage plus the allowed ΔVclamp plus some margin to provide for reliable operation. For example, if Vrfl = 120V and ΔVclamp is held to 30V, then a 200-V rating still has 50 V of margin to its rating. Even though the clamp cap is riding on a high voltage bulk rail, its working voltage is usually not that high.

I hope this helps you to understand the design decisions and calculations that need to be made to arrive at a reasonable starting point. Even after “paper design” iterations, sometimes further refinement is needed while evaluating the prototype performance due to parasitic parameters unknown prior to building a prototype, such as leakage inductance and Coss variability.

Regards,
Ulrich

Thanks for the complete reply, Ulrich, and for your helpful Mathcad worksheet.  That has really helped me get an initial design going.  It's a great help for those of us that are less than expert on the IC, but that can be a double-edged sword.  It means that as soon as something doesn't work right you need to do a lot of digging to figure out what's going on.

I'm familiar with the tradeoffs regarding switcher frequency, but it wasn't clear to me that eqn (23) is actually where you specify your desired minimum fSW.  I thought that was derived somewhere else.  The companion worksheet to yours (from Pei-Hsin Liu) provides some nice graphs of fSW variation, but I didn't see any discussion of the fSW range in the data sheet.

Thank you also for the clarification on the clamp capacitor voltage rating.  I'll put that in my copy of your worksheet.

I discovered my error in the NPS calculation, too.  Since the min and max were coming out inverted, I needed to increase the VDRM_rating figure for my SR MOSFET.  Pretty simple once you understand what's going on!

I have found that data sheets which provide general formulas (like the UCC28780 does) are greatly enhanced when actual numbers from a sample design are also shown.  This gives an additional check on the formula variables, allows you to make sure your units are right, and helps you to figure out the meaning of the formula variables when it's not clear.  TI has done an impressive job documenting such a complex IC, but I think it could benefit from something like that.