CLA 2p2z strange error in output (goes to infinity)

Here is the linker code for 2p2z CLA. 

Niclas,

1. Make sure the "Out" variable is in a CLA accessible space

2. Also note, we do have CLA C compiler now for CLA and things may be much more easy to write and debug with it.. we also have the dp lib with CLA C.

Thanks for the reply! "Out" is accessible to the CLA, but I think this is related to memory somehow. The issue was gone after I added more code not related to 2p2z. But now the 2p2z is acting strangely again when I continue to add more things in the program.

I looked at the C-code DP lib for CLA but it seems to take more cycles for computations. I would prefer to use the assembly macros if possible.

Here is the code inside my linker file. Can you see if anything is bad?

MEMORY
{
PAGE 0 :
   /* BEGIN is used for the "boot to SARAM" bootloader mode   */

   BEGIN                : origin = 0x000000, length = 0x000002
   RAMM1                : origin = 0x000480, length = 0x000380     /* on-chip RAM block M1 */
   RAML0L1              : origin = 0x008000, length = 0x000C00
   RAML3                : origin = 0x009000, length = 0x000C18
   CLARAM				: origin = 0x009C19, length = 0x0003E8
   RESET                : origin = 0x3FFFC0, length = 0x000002
   IQTABLES             : origin = 0x3FE000, length = 0x000B50     /* IQ Math Tables in Boot ROM */
   IQTABLES2            : origin = 0x3FEB50, length = 0x00008C     /* IQ Math Tables in Boot ROM */
   IQTABLES3            : origin = 0x3FEBDC, length = 0x0000AA	 /* IQ Math Tables in Boot ROM */

   BOOTROM              : origin = 0x3FF27C, length = 0x000D44


PAGE 1 :

   BOOT_RSVD            : origin = 0x000002, length = 0x00004E     /* Part of M0, BOOT rom will use this for stack */
   RAMM0                : origin = 0x000050, length = 0x0003B0
   dataRAM              : origin = 0x008C00, length = 0x000400		/* RAML2 */
   CLA_CPU_MSGRAM      	: origin = 0x001480, length = 0x000080
   CPU_CLA_MSGRAM      	: origin = 0x001500, length = 0x000080
}


SECTIONS
{
   /* Setup for "boot to SARAM" mode:
      The codestart section (found in DSP28_CodeStartBranch.asm)
      re-directs execution to the start of user code.  */
   codestart        : > BEGIN,     PAGE = 0
   ramfuncs         : > RAMM1      PAGE = 0
   .text            : >> RAML0L1 | RAML3,   PAGE = 0 /* default code section */
   .cinit           : > RAMM1,     PAGE = 0 /* initialised variables */
   .pinit           : > RAMM1,     PAGE = 0 /* global constructor table */
   .switch          : > RAMM1,     PAGE = 0
   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */

   .stack           : > RAMM0,     	 PAGE = 1 align(2) /* stack: even word alignment */
   .ebss            : > dataRAM,     PAGE = 1
   .econst          : > dataRAM,     PAGE = 1
   .esysmem         : > dataRAM,     PAGE = 1

   IQmath           : > RAML0L1,   PAGE = 0
   IQmathTables     : > IQTABLES,  PAGE = 0, TYPE = NOLOAD

   Cla1Prog         : LOAD = CLARAM,
                      RUN = CLARAM,
                      LOAD_START(_Cla1funcsLoadStart),
                      LOAD_SIZE(_Cla1funcsLoadSize)
                      RUN_START(_Cla1funcsRunStart),
                      PAGE = 0

   Cla1ToCpuMsgRAM  : > CLA_CPU_MSGRAM,   PAGE = 1
   CpuToCla1MsgRAM  : > CPU_CLA_MSGRAM,  PAGE = 1

  /* Uncomment the section below if calling the IQNexp() or IQexp()
      functions from the IQMath.lib library in order to utilize the
      relevant IQ Math table in Boot ROM (This saves space and Boot ROM
      is 1 wait-state). If this section is not uncommented, IQmathTables2
      will be loaded into other memory (SARAM, Flash, etc.) and will take
      up space, but 0 wait-state is possible.
   */
   /*
   IQmathTables2    : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
   {

              IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)

   }
   */
   /* Uncomment the section below if calling the IQNasin() or IQasin()
      functions from the IQMath.lib library in order to utilize the
      relevant IQ Math table in Boot ROM (This saves space and Boot ROM
      is 1 wait-state). If this section is not uncommented, IQmathTables2
      will be loaded into other memory (SARAM, Flash, etc.) and will take
      up space, but 0 wait-state is possible.
   */
   /*
   IQmathTables3    : > IQTABLES3, PAGE = 0, TYPE = NOLOAD
   {

              IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)

   }
   */

}


SECTIONS
{
	/*************       DPLIB Sections C28x      ************************/
	/* ADCDRV_1ch section */
	ADCDRV_1ch_Section				: > dataRAM				PAGE = 1

	/* ADCDRV_4ch section */
	ADCDRV_4ch_Section				: > dataRAM				PAGE = 1

	/* CNTL_2P2Z section */
	CNTL_2P2Z_Section				: > dataRAM				PAGE = 1
	CNTL_2P2Z_InternalData			: > dataRAM				PAGE = 1
	CNTL_2P2Z_Coef					: > dataRAM				PAGE = 1

	/* CNTL_3P3Z section */
	CNTL_3P3Z_Section				: > dataRAM				PAGE = 1
	CNTL_3P3Z_InternalData			: > dataRAM				PAGE = 1
	CNTL_3P3Z_Coef					: > dataRAM				PAGE = 1


	/*DLOG_4CH section */
	DLOG_4CH_Section				: > dataRAM				PAGE = 1
	DLOG_BUFF						: > dataRAM				PAGE = 1

	/*MATH_EMAVG section */
	MATH_EMAVG_Section				: > dataRAM				PAGE = 1

	/*PFC_ICMD section*/
	PFC_ICMD_Section				: > dataRAM				PAGE = 1

	/*PFC_INVSQR section*/
	PFC_INVSQR_Section				: > dataRAM				PAGE = 1

	/* PWMDRV_1ch driver section */
	PWMDRV_1ch_Section				: > dataRAM				PAGE = 1

	/* PWMDRV_1chHiRes driver section */
	PWMDRV_1chHiRes_Section			: > dataRAM				PAGE = 1

	/* PWMDRV_PFC2PhiL driver section */
	PWMDRV_PFC2PhiL_Section			: > dataRAM				PAGE = 1

 	/* PWMDRV_PSFB driver section */
	PWMDRV_PSFB_Section				: > dataRAM				PAGE = 1

	/* PWMDRV_DualUpDwnCnt driver section */
	PWMDRV_DualUpDwnCnt_Section		: > dataRAM				PAGE = 1

	/* PWMDRV_ComplPairDB driver section */
	PWMDRV_ComplPairDB_Section		: > dataRAM				PAGE = 1

	/* ZeroNet_Section  */
	ZeroNet_Section					: > dataRAM				PAGE = 1

	/*************       DPLIB Sections CLA      ************************/
	/* ADCDRV_1ch_CLA section */
	ADCDRV_1ch_CLA_Section    		: > CPU_CLA_MSGRAM 	PAGE = 1

	/* ADCDRV_4ch_CLA section */
	ADCDRV_4ch_CLA_Section    		: > CPU_CLA_MSGRAM 	PAGE = 1

	/* CNTL_2P2Z_CLA controller sections */
	CNTL_2P2Z_CLA_Section     		: > CPU_CLA_MSGRAM 		PAGE = 1
	CNTL_2P2Z_CLA_InternalData 	    : > CLA_CPU_MSGRAM  	PAGE = 1
	CNTL_2P2Z_CLA_Coef				: >	CPU_CLA_MSGRAM		PAGE = 1

	/* CNTL_3P3Z_CLA controller sections */
	CNTL_3P3Z_CLA_Section     		: > CPU_CLA_MSGRAM 		PAGE = 1
	CNTL_3P3Z_CLA_InternalData 	    : > CLA_CPU_MSGRAM  	PAGE = 1
	CNTL_3P3Z_CLA_Coef				: >	CPU_CLA_MSGRAM		PAGE = 1

	/*MATH_EMAVG_CLA sections */
	MATH_EMAVG_CLA_Section			: > CPU_CLA_MSGRAM		PAGE = 1
	MATH_EMAVG_CLA_InternalData		: > CPU_CLA_MSGRAM		PAGE = 1

	/*PFC_ICMD_CLA sections*/
	PFC_ICMD_CLA_Section			: > CPU_CLA_MSGRAM		PAGE = 1
	PFC_ICMD_CLA_InternalData		: > CPU_CLA_MSGRAM		PAGE = 1

	/*PFC_INVSQR_CLA sections*/
	PFC_INVSQR_CLA_Section			: > CPU_CLA_MSGRAM		PAGE = 1
	PFC_INVSQR_CLA_InternalData		: > CPU_CLA_MSGRAM		PAGE = 1

	/* PWMDRV_1ch_CLA driver section */
	PWMDRV_1ch_CLA_Section    		: > CPU_CLA_MSGRAM 	PAGE = 1

	/* PWMDRV_1chHiRes_CLA driver section */
	PWMDRV_1chHiRes_CLA_Section		: > CPU_CLA_MSGRAM 	PAGE = 1

 	/* PWMDRV_PFC2PhiL driver section */
	PWMDRV_PFC2PhiL_CLA_Section		: > CPU_CLA_MSGRAM 	PAGE = 1

 	/* PWMDRV_PSFB_CLA driver section */
	PWMDRV_PSFB_CLA_Section	 		: > CPU_CLA_MSGRAM 	PAGE = 1

	/* PWMDRV_DualUpDwnCnt_CLA driver section */
	PWMDRV_DualUpDwnCnt_CLA_Section	 : > CPU_CLA_MSGRAM		PAGE = 1

	/* PWMDRV_ComplPairDB_CLA driver section */
	PWMDRV_ComplPairDB_CLA_Section	 : > CPU_CLA_MSGRAM		PAGE = 1

	/* ZeroNetCLA_Section  */
	ZeroNetCLA_Section				 : > CPU_CLA_MSGRAM 	PAGE = 1


}

Can you post your map file?

I see you are exclusively using the message RAMs for the CLA, they are tiny.

Ok so there is no way to use [ 0x009000, length = 0x001000 ] for anything else than CLA? I have been trying to split it, since it is a lot of ram not being used right now. Thanks for the reply!