TPS23523: one question about the delay time of Power Good in TPS23523

Oliver Ou

Intellectual 2845 points

Part Number: TPS23523

Hi,

From below electrical table of TPS23523, the delay time of power good from low to high.

Is it measured from Gate=0 to PG=high?

if Gate changed sever times with 32ms, power good would not change?

Can you give more comments for the inserting delay?

Thanks.

over 7 years ago

0 Brian Daugherty over 7 years ago

TI__Expert 5940 points

Oliver

It is measured from Vgate fully enhanced at 10v to PG going low. Otherwise, with soft start, it would be a very long time from Vgate = 0v.

Brian

0 Oliver Ou over 7 years ago in reply to Brian Daugherty

TI__Intellectual 2845 points

Hi Brian,

Thanks a lot for your clarification. How about below question?

'Gate changed sever times with 32ms, power good would not change?'

Regards,

Oliver Ou

0 Brian Daugherty over 7 years ago in reply to Oliver Ou

TI__Expert 5940 points

Not sure what your question is. Do you mean you have a 32ms rise time? PG is after gate reaches 10v, which is after the 32ms rise time

Brian

0 Oliver Ou over 7 years ago in reply to Brian Daugherty

TI__Intellectual 2845 points

Hi Brian,

The 32mS is measured from Vgate fi;;u enhanced at 10G to PG going low.

That means PG signal has 32mS delay. is it right?

If the Vgate has changed then recovered for some reason with 32mS delay time.

The PG would keep previous status and would not change? is it right?

Thanks.

0 Brian Daugherty over 7 years ago in reply to Oliver Ou

TI__Expert 5940 points

Oliver,

the delay is per the EC table in the DS. It depends on when Vgate reaches 10v. That is impacted by any gate capacitance that is added.

Brian

Power management

Power management forum

TPS23523: one question about the delay time of Power Good in TPS23523