BQ76940: BQ76940

Hi User,
1. Yes, those are the cells recommended to short when reducing the cell count to 13 cells. The short must be external to the device, and you still need an input filter circuit. See the application note www.ti.com/.../slua810.pdf figure 4 for an example of reducing cell count. While it is a different cell count and different member of the family it should be helpful for understanding.
2. Either will work, N-channel would seem to offer less stress on the device inputs. See www.ti.com/.../slua749 figure 18 compared to figure 19.
3. See the "top 10" apnote above section 4.
4. Yes, it is an integrating converter.
5. I expect the battery voltage measurement to update with each cell voltage, the documentation does not specifiy. See the data sheet section 7.3.1.1.6.
6. The bq76930 and bq76940 have multiple cell groups which communicate on the timing shown.
7. The expectation is that if 1 cell is balanced 2 or 3 capacitors may be at an alternate voltage and must settle. If 2 cells are balanced all the capacitors will be at a different voltage and the filter would take longer to settle because more inputs are moving. You may not be so concerned that it settle to x% of its final value which would be from its time constant but to y mV which would depend on how much it needs to move. However this might be an incorrect assumption, you could simulate to determine times.
8. See the "top 10" apnote figure 6. Assume a 4V cell. When VCb and VCc pull together, the resistances are approximately equal and the voltage will be approximately 2V above the lower cell providing 2V for Vgs. If you select a FET with an RDSON specification at 2.5V, you don't know what its RDSON will be at 2V. You can look at the typical curves in the FET data sheet and you may be happy with that answer. Or you may choose to pick a FET with an RDSON specification at 1.8V, then you may be more confident in the RDSON of the FET.

Question 3 : If external balance use P-FET, What is the principle of circuit design? What's the current flow?
If external balance use P-FET, how to turn on P-FET ? What's the trigger signal?
Question 5 : Battery voltage measurement requires 8 cycles ( 2 s), Is it for the average of every cell voltage?
I expect the battery voltage measurement to update with each cell voltage, the documentation does not specifiy. See the data sheet section 7.3.1.1.6. What is the name of the document?
Question 8 : 1.8V refer to the voltage of RDSON? Turn on FET to balance, the voltage of FET is ½ the cell voltage, and the voltage of balance resistance is also ½ the cell voltage?

New problems:
1: There are three diodes between BATT+ and BAT,VC10 and VC10x,VC5 and VC5x ,What does the diode do?
The diodes prevent over voltage of certain inputs. See www.ti.com/.../slua749 figure 20,
Can you explain it in more detail? I read it, I don't quite understand.
2: The "top 10" refer to " The input filter must settle within the 12.5 ms or there will be voltage error in the cell measurement", The input filter must settle within the 12.5 ms, How to guarantee? Related to external Rc input resistors and the Cc filter capacitors?
Thank you very much for the reply.

Hi User,
Q3: Read the "top 10..." section 4. See figure 5 for P-channel instead of figure 6.
Q5: The bq76940 data sheet should be accessible from the product folder at the link left, or www.ti.com/.../bq76940
Q8: When the gate of the FET sees 1/2 of the cell voltage you want the FET to turn on fully. If the FET is on with an RDSON of 0.2 ohm and you have a cell balance resistor of 100 ohm, the cell voltage will distribute across these 2 in series, most voltage will be across the balance resistor. Check the RDSON of your FET, in many cases you might neglect the voltage drop across the FET.
New1: If you apply a step to the top cell, the small input filter capacitor will charge quickly and VC15 will have its full voltage quickly. The power supply filter capacitor must be large so it will charge slowly. Rather than create a specification for how much voltage is allowed between the input and the power pin, the data sheet just says to use the diode.
New 2: The differential filter will have 6 inputs for the bottom group (5 cells) and 5 inputs for the upper groups (4 cells). It would be a complicated equation. You could simulate to see the settling time, or simply build it and if you see undesired voltage artifacts during balancing decrease the capacitor sizes. The capacitors must be large enough to keep damaging transients out of the IC, so there is a tradeoff, you must make that decision for your system.

Hi WM:
First of all,thank you very much for answering my question,help me a lot.Today I also have some questions.
Q3(It was mentioned yesterday): I have read it ,but I don't quite understand.Can you explain it in more detail? how to turn on P-FET ? What's the trigger signal?
New questions:
1: The "top 10" refer to " REGSRC Supply" ,the diode-resistor pair is placed in the source path or in the D path ?which is better? why?
2: The "top 10" refer to Figure 22~24, Does it need to be considered in practical applications?
3: The "top 10" refer to " When multiple FETs are used, a small resistor to the gate of each FET may be desired, check with your
FET supplier. Switching speed will slow with multiple FETs due to the added capacitance. When faster switching is needed a driver will be needed for the FET gate." why?
4: Subsection 6 of The "top 10" , "FET Drive" refer to " The pull-up resistance may be calculated from the rise time conditions in the datasheet and is approximately 5 kΩ." 5KΩ How to calculate？
5: Subsection 6 of The "top 10" , "FET Drive" refer to “D2 should be selected so that it does not conduct when Q1 is on with PACK- at the battery- voltage” D2 does not conduct？how to realize ? There should be a small current, because there's a path to the CHG.
Thank you very much for the reply.