TPS7A63-Q1: About internal delay from EN->High to start output of Vout

Hi Kato,

This time is 116 us typically. We do not have min/max data on this time.

Very Respectfully,
Ryan

Hi Kato-san,

When the LDO is disabled, much of the internal circuitry is turned off in order to conserve power. When the LDO is enabled, the internal circuitry is turned on in a defined order so that everything turns on properly. As a result of the propagation delay to detect that EN transitioned to logic high and the internal power-up sequencing, there is typically a 116 us delay from the EN signal transitioning to Vout beginning to rise.

Very Respectfully,
Ryan