This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

BQ76PL455A: EQn Pin Idle State when IC not energized

Part Number: BQ76PL455A

Hello together,

I would like get information about EQ pins of IC under listed conditions.

- VIO,VP and VDIG pins supplied with external supply and let's assume external supply in shutdown mode and these pins voltage is 0V. So, BQ76PL455A is not energized and only Vsense pins are alive.

- TOP pin connected to GND with 100K resistor. 

- NPNB pin is floating.

- Passive balancing circuit established with nmos. 

Under these conditions, does EQ-(n) pin  connected to Vsense-(n-1) pin  stably ? What is the connection resistance value ? In addition, what is passive balance register idle values after production?

I couldn't be sure about these topics. Because, there are two different applications with pmos and nmos in the datasheet and there is not any detailed information about EQ pins. (Page 111) 
In my opinion, EQ-(n) pin have to be connected to Vsense-(n) pin in idle state for pmos application. So, idle states of EQ pins after production is too important to which type of mosfet i used.

I am kindly waiting your replies.

  • Hi User,

    The PL455 should only use an NMOS balancing FET. If you follow our EVM schematic (TIDA-00717), the FET used here is a good choice.

    When balancing, there is a driver that will force the NFET gate to roughly the cell voltage. This will ony occur when the corresponding bit CBENBL register is set to "1" by the MCU. All other times the driver pulls to the cell below as you mentioned (this is also the default), keeping the MOSFET off.
  • Hi David,

    Thank you for explanation and the EVM schematic was very helpful. I would like to remark that the figure 35 (cell connections with pmos) in the BQ76PL455 data sheet is confusing.  Because, figure 28 shows n-mos passive balance architecture, after few pages figure 35 shows p-mos passive balance architecture. There is not any further explanation about these two figures. It would be better if there is detailed explanation. 

    Thanks.