I would like get information about EQ pins of IC under listed conditions.
- VIO,VP and VDIG pins supplied with external supply and let's assume external supply in shutdown mode and these pins voltage is 0V. So, BQ76PL455A is not energized and only Vsense pins are alive.
- TOP pin connected to GND with 100K resistor.
- NPNB pin is floating.
- Passive balancing circuit established with nmos.
Under these conditions, does EQ-(n) pin connected to Vsense-(n-1) pin stably ? What is the connection resistance value ? In addition, what is passive balance register idle values after production?
I couldn't be sure about these topics. Because, there are two different applications with pmos and nmos in the datasheet and there is not any detailed information about EQ pins. (Page 111)
In my opinion, EQ-(n) pin have to be connected to Vsense-(n) pin in idle state for pmos application. So, idle states of EQ pins after production is too important to which type of mosfet i used.
I am kindly waiting your replies.