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TPS735: Fixed 3v3 GND pin 3 limit from/to bottom PAD current flow

Genatco
Guru 55913 points
Part Number: TPS735

Datasheet does not specify if pin 3 is internal connected to bottom pad. If not internally bonded connected what of MAX current between pin 3/pad not being listed in AMR? What is the resistance pin 3 to bottom pad also not listed in AMR? Have to ask that question as it requires laboratory grade DMM to measure that low of resistance, if any.

Condition: Bottom pad has PCB bottom foil VIA's route analog ground and top foil digital ground path pin 3. That is to say top foil digital ground is partially isolated from bottom side analog ground via strategically place 20mohm ferrite. DMM indicates 4.4mv drop across grounds isolation ferrite thus indicates 220ma of LDO 3v3 current flow sourced from +5vdc feeding LDO pins 4/6.

Can we assume the two grounds bond inside the TPS pin 3 using two placed VIA of the VSON6 bottom pad? If pin 3 to pad is not bonded on the die perhaps bottom pad did not join in reflow?

  • 0
    TI__Expert 4435 points
    Hi,

    Thermal pad (bottom pad) is usually not down bonded inside the package.

    I checked the bond diagram for TPS735 and there is no bond wire from thermal pad to the IC ground. Thermal pad is used to conduct heat out of the package, not to provide an electrical ground path.

    The silicon substrate is glued to the leadframe, so there is an insulative layer of silicon between the exposed thermal pad (bottom pad) and the IC ground. You should not expect an electrical path from the ground pin to the thermal pad (bottom pad).
  • 0 in reply to Eric.Preiss
    Guru 55913 points
    Hi Eric,

    Thanks a bazillion for such an informative answer, so we can exclude that internal bond idea from transient analysis entirely. Perhaps the datasheet should mention such rather than simply state to connect pad to VIA ground. And we didn't check before installing but will test the next one to be sure.

    Some how a transient voltage on input seemingly causes 3v3 to rise over 3.5v or more. Filters used: 0.01uf pin 2, 3.3uf pin 1, 0.1uf pin 6 . The supply PIN6/5EN source is located 4" across PCB to a Rohm 1.5Mhz +5vdc buck switcher. Perhaps adding a ferrite bead near pin 6 in the supply path could help improve output transient response? We now have an 0402 Zero ohm resistor there. Yet the 3v3 ripple under 50mv does not look that bad until a PWM inverter transient occurs see several inverter bumps ride on top of 3v3.
  • 0 in reply to Genatco
    TI__Expert 4435 points
    Hi,

    I added the TPS735 datasheet to our list to revise regarding the thermal pad. On all new and revised datasheets we will clearly state that thermal pad is not bonded to IC ground, it is a thermal path only.

    A series ferrite bead on the LDO input will help attenuate switching spikes from the Rohm buck switcher before they go through the LDO. The LDO's bandwidth is not high enough to attentuate switching spikes from a switching regulator. PSRR of the LDO is good for reducing ripple, but not switching spikes. Do you have a PWM inverter on the input to the Rohm buck switcher?

    Can you share any scope shots? I assume you are using the fixed 3.3 V TPS735? The caps on the LDO pins are within recommended limits.
  • 0 in reply to Eric.Preiss
    Guru 55913 points
    Hi Eric,

    Been tied on few other issues, have not had time to make captures but Rohm buck is at the moment connected 24v off line with 1 other Rhom bucking +15. Will certainly consider captures when I get this running again and post them here.

    Many thanks!