Dear all,
Can I think 'VOUT > VSET_DCDC + 6~10V' as 'OUTx voltage > LOW~MID_COMP + 6~10V'?
I think like this because Vout is regulated by feedback from OUTx voltage in order to operate between headroom window.
Best regards,
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Dear all,
Can I think 'VOUT > VSET_DCDC + 6~10V' as 'OUTx voltage > LOW~MID_COMP + 6~10V'?
I think like this because Vout is regulated by feedback from OUTx voltage in order to operate between headroom window.
Best regards,
Yamamoto-san,
Your understanding is correct.
For #3 case above, as an example, if max Vout is set to 25V by FB resistor divider, and Vin is higher than 35V, it will cause much higher FB voltage by high Vin resulting high Vout, and trigger OVP fault as well.