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TPS65217: Schematic recommendations if DCDC3 is not utilized?

Christopher Chorey
Prodigy 170 points
Part Number: TPS65217

In my implementation using this device, I do not have a need for the DCDC3 Step-Down Converter.  What is the recommendation to handle this situation?  Can the Output Inductor and Capacitors be DNI'd? or should they be placed anyway?  We would prefer to save the cost of the components.

  • 0
    TI__Genius 17380 points
    Hi Chris,

    I have assigned this to the device expert but I believe that as long as you tie VDCDC3 to a greater than or equal to voltage that is enabled before it, it should register as "power good" and not cause a fault. This is described in the schematic checklist: www.ti.com/.../slva686b.pdf
  • 0 in reply to Kevin LaRosa
    TI__Mastermind 30280 points
    Kevin is correct.

    In addition, the schematic checklist recommends that you leave L3 as Floating (NC, or no connection) and pull VIN_DCDC3 directly up to VSYS. No inductors or capacitors required.
  • 0 in reply to Brian Berner
    Prodigy 170 points

    Thank you, appreciate the quick response!

  • 0 in reply to Brian Berner
    Intellectual 613 points
    Hi Kevin & Brian,

    One question:

    By default, this DCDC3 output is supposed to comes with 1.1V. Now, tying the VDCDC3 pin (Feed back pin) to VSYS will immediately disable the DCDC3 during power up, correct?

    There will not be a condition where, the output of the DCDC converter trying to follow the Feedback voltage continuously.

    Is this understanding correct?

    Thanks and regards,
    Paul
  • 0 in reply to Paul Chacko
    TI__Mastermind 30280 points
    Paul,

    The DCDC3 converter will not be disabled this way. It will still be switching, so you should pull up VDCDC3 feedback pin to a voltage >1.1V but not much higher. A 1.8V LDO would work, or maybe the DDR voltage.

    The reason for tying it to a higher voltage is so that the PGOOD signal will still go high. Otherwise, it will not go high and result in the whole system Resetting in a continuous loop.

    Since no current is drawn through a load ( output inductor-capacitor-load), the current draw will be negligible. DCDC3 can be disabled via I2C when the system is up and running in the ACTIVE state. This should be added to the initialization routine and any time time the Registers of the TPS65217 PMIC are reset (for example, coming out of Sleep/OFF states.
  • 0 in reply to Brian Berner
    Intellectual 613 points

    Brian,

    Thanks for the response.Just wanted to clarify one more thing.

    Normally, the feed back loop operation should be in such a way that the Out put voltage is equal to the programmed output voltage as per the PMIC internal register for DCDC3. Said that, Feedback voltage = output voltage, the system should continuously try to make the output voltage as 1.1V (because of the default setting) until, the SW comes and modifies the internal register.

    If we are tying to any other voltage (1.8V or 1.35V), will the system be in an infinite loop trying to make the output voltage to 1.1V? Otherwise, DCDC3 should detect an unregulated output and disable the DCDC3.

    Is my understanding correct?

    Thanks and regards,

    Paul

  • 0 in reply to Paul Chacko
    TI__Mastermind 30280 points
    Paul,

    From the perspective of the system, the only requirement is that VDCDC3 > DCDC3 voltage setpoint (1.1V) in order for PGOOD to go high.

    Until DCDC3 is disabled, yes, it will try to generate 1.1V by switching because it always sees 1.35V (or 1.8V) at the VDCDC3 feedback pin.

    But since L3 will be floating, there is nowhere for the current to go when the high-side FET turns on. So, the current consumption is coming from the gate driver and the feedback resistor path, not the actual DC-DC path. All of the current consumed is low, but can be reduced further by disabling DCDC3 after the system is up and running.
  • 0 in reply to Brian Berner
    Intellectual 613 points

    Thank you Brian.

    So your recommendation is to connect the Feedback pin to some 1.8V than connecting to another 1.1V (DCDC2) available from the same PMIC (which is being used in the system). Correct?

    Regards,

    Paul

  • 0 in reply to Paul Chacko
    TI__Mastermind 30280 points
    Paul,

    My suggestion is to connect VDCDC3 (Feedback pin for DCDC3) to DCDC1.

    From a sequence timing perspective, connecting VDCDC3 to DCDC1, LDO1, and DCDC2 are all viable options. These rails should all be in regulation before DCDC3 is enabled and ensure PGOOD signal is not affected.

    Connecting to DCDC2 will probably work, but why risk it? There is no over-voltage condition on the rails in the TPS65217 so the feedback voltage at VDCDC3 does not need to be inside a window. It simply needs to be above a line. Why not put it farther above the line?