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VLDO1 doesn't come out with VSYS and the device cannot enter "active" mode

user5308372
Prodigy 30 points

Dear experts,

We met power-up issue with TPS65217C. We can measure correct SYS voltage after sourcing power to VBAT(3.6V) or AC(5V).

We connect SYS to VIN_LDO as recommanded. From the datasheet, LDO1 voltage should come out directly with SYS voltage, but we cannot measure that. (There is no loading on VLDO1)

When we hold PB_IN low, we saw 5s + 3s cycle which looks similar to "Wait PWR_EN timeout" and "PB_IN reset":

-in 5s period -> LDO1 output is 1.8V, LDO_GOOD is high, PGOOD is low.

-in 3s period -> LDO1 output is 0V, LDO_GOOD is low, PGOOD is low.

-once we pull PWR_EN high, the LDO1 output drop to 0V.

-if we pull PB_IN high, after this 5s period, LDO1 output drop to 0V and never go back to 1.8V.

 Could you help us on this or let us know if you need extra INFO or experiment. Thanks very much.

  • 0
    TI__Genius 10885 points
    PB_IN has a 50ms deglitch time and does not need to be held low for the 5 second period. PWR_EN must be asserted high before the 5 second timeout, and can even be asserted before the PB_IN event.

    If PWR_EN is not asserted within 5 seconds, the device will return to off mode, and LDO1 will be disabled. Figure 24 in the datasheet has further details on the internal state machine.

    Other faults such as a UVLO event on the input or overtemperature condition could also lead the device to turn off.

    Best Regards,
    Rick S.
  • 0 in reply to Richard Solarski
    Prodigy 30 points
    Hi Richard,
    Thanks for the reply.
    We have tried asserting high on PWR_EN but once that happen, we lose all normal output such as LDO1, BYPASS, PGOOD, etc.
    Is there any other faults can cause the device to turn off? We are sure we don't have UVLO and over-temperature issue.
  • 0 in reply to user5308372
    TI__Mastermind 30310 points
    If you perform an experiment and capture these channels on an oscilloscope then it will be easier to debug:
    VSYS, VLDO1, PB_IN, and PWR_EN.

    You will need to set the horizontal scale to 1s/div to capture 10s in a single window.

    In a normal power-on sequence, PWR_EN will go from high-to-low within ~100ms and must stay high.

    A typical fault condition would be a short to GND on a power rail or an overcurrent that is not a short due to large inrush current from a load.

    If you never see PGOOD go high, then one or more rails has a fault condition. The timing diagram you chared shows LDO_PGOOD is high when LDO1 is enabled. This only means that the LDO1 rail is not experiencing a fault.
  • 0 in reply to Brian Berner
    Prodigy 30 points

    Hi Brian,

    Thanks for your help.

    We captured waveform with oscilloscope but since the max timing scale we have is 250ms so we cannot capture with 1s/div.

    -LDO1 start to output 1.8V when PB_IN fall, but return to 0V after PWR_EN assert high.

    -Why LDO_GOOD and PGOOD start and end at high?

  • 0 in reply to user5308372
    TI__Mastermind 30310 points
    I am going to ask you the same question: why are PGOOD and LDO_PGOOD high before the PB_IN push button is pressed?

    LDO_PGOOD can be high when only LDO2 is enabled and in regulation at 3.3V, but PGOOD should not be high when LDO1 is low.

    Can you also measure VIO and determine if VIO is applied externally before the Battery is connected?
    This would effectively allow any of the I/Os to go when the PMIC is off and produce this strange behavior.

    It would also pull SYS and BAT up to ~1-2V when no voltage is applied at the BAT pin directly. This is the most obvious way to see that VIO was applied to the PMIC too early.