Dear Texas team,
This is the continuation from this post: https://e2e.ti.com/support/power_management/non-isolated_dcdc/f/196/p/645543/2381672#2381672 which is locked but not solved yet. Unfortunately Argentina official agent in charge of making EMC test is hiper slow :( so we have not any probe that the problem is truly solved.
We are desingning a new revision of the PCB with the Anthony suggestions but now we have a doubt. Texas layout example for TPS has not ground plane on the bottom layer under the inductors and of course our desing is based on this example. We want to know if it's really harmful to put it because it would block the EMC in that direction.
Hope you can help us.
Best regards,
Bruno