UCC27531: UCC27531 Driver current and MOS_G Waveform

Hello User,

I'm an applications engineer with the High Power Drivers team and can help you with your question.

Could you please share your layout along with a capture showing the Vds of your FET when this dip occurs? This will help gain a better understanding of the cause of the dip.

Best Regards,
John

Hi User,

Thanks for your question, I work with John and will also help out with this post.

The dip appears to be long so perhaps the VDD power supply needs to be investigated. Can we also see whats happening to Vdd during the dip?

Its possible that when the switch turns on the GND/source pin is seeing a bounce. If the FET reference is bouncing its possible that the gate is bouncing with it which is ok as long as the Vth is met. Making sure the driver ground and FET source are close to the IC and at the same potential is important.

also, can you tell me what gate clamping diode you are using? and what is the purpose for the 2nF gate cap?

Thanks,

Dear :

 modified my waveform.   I  didn't draw pcb layout and make the test by hand.    I Use normal Zener Diode and the 2nf gate cap to restrain Miller effect.
I have a try by delete the gate cap ,but the wave  the same.
i guess maybe the drive current a little small  cause the mosfet (IRF1404) Total gate charge =200nc.  i'm not sure the gate resistor suitable ? 

I have a question,  does miller platform can cause the dip. Thanks a lot.

D_waveform:

G_Waveform:

Hi user,

Thanks for your update. can you confirm if D_waveform = drain and G_waveform = gate? its hard to tell whats going with the waveforms not on the same plot. But if D_waveform is the drain waveform when the LS turns off then...

the miller region happens when the drive voltage waveform is at about 5V. This miller affect can be seen as the quick dip in the G_waveform - it is overcome as the drain voltage starts to swing. Since the drain voltage reaches the rail ok, miller is not the issue.

After turn off, and back EMF, The longer dip on the Drain waveform may be due to ground bounce from large FET source inductance. As the LS switch turns off, if the drain voltage goes high too quickly there ends up being more load current flowing through the FET. If there is a large source inductance and large loop areas (from breadboard for example) the load current will be held up by this inductance creating a voltage difference between FET source and GND pin. This spike on the source pin is manifesting itself as a dip on the gate pin when WRT to GND.

To confirm ground bounce you can probe FET source - GND to see if they are the same potential throughout the switching period. Make sure to measure as close as possible to the FET and IC pins.

To minimize ground bounce - tighten up loop areas. As you switch the fet on/off the loop area changes from diode/motor to the larger loop supply/driver/fet/motor. This change in loop area will create a change in flux so voltage is induced. Since the return path is common in the 2 loops a voltage will appear on the return path. Therefore the loop areas should be similar to avoid a large change in flux. From Faradays law, if you increase the time it takes to switch from the big loop to the small loop or FET off time you can reduce the induced voltage, therefore increasing R_gate_off will help as well.

Thanks,