TLC5955: Display timing reset?

Derek Burns

Part Number: TLC5955

I have some questions regarding the use of the "Display Timing Reset" feature of the TLC5955.

1. It is my understanding that, in order to invoke this feature, all I need to do is pull LAT high while GSCLK is in a low state? Am I correct?

2. As long as I don't send in any new data through SIN/SCLK between two separate LAT pulses, will the grayscale/control data remain unchanged on that second pulse?

I mainly ask this because a project that I am working on requires some particular timing constraints that involve higher PWM frequencies than this chip provides by default. I believe that I can increase this apparent frequency by scaling down the duty cycle, and then just resetting the GS counter early. Say I wanted twice the refresh rate. I would scale my 16-bit GS value by 1/2, and then reset the GS counter once it reaches 32,768 steps in.

over 7 years ago

0 Kenneth Du over 7 years ago

TI__Genius 14295 points

Hi, Derek,

You are correct. If the display timing reset bit (TMGRST) in the control data latch is 1, the grayscale counter initialized at the LAT signal is
input for a grayscale data write.

Since the GS counter is reset once it reaches 32768 steps, the 16 bit GS value is decreased to 15 bit.

If the SIN is the same, the LAT pulse just write the same data to the register, which won't change your grayscale and control data.

If you think this answers your question, please help to click "Resolve".

Thanks.
Regards,
Kenneth

0 Derek Burns over 7 years ago in reply to Kenneth Du

Prodigy 20 points

So if I hold SCLK low then the internal shift register won't change, correct?

0 Kenneth Du over 7 years ago in reply to Derek Burns

TI__Genius 14295 points

That's correct.

If SCLK is low, no data will be shifted to the device.

Thanks.
Regards,
Kenneth

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TLC5955: Display timing reset?