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UCC28950: UCC28950 SR Design Questions

Wei-Hao Chen (TW-FAE)
Expert 3260 points
Part Number: UCC28950

Hi team,

My customer is having some questions regarding how to design the SR circuit for UCC28950. The input is universal AC and output is 115V/15.6A.

The questions are:

1. For this application is it better to use full-bridge or center tapped full wave rectifier? What are the difference apart from the peak reverse voltage is doubled for center-tapped full wave rectifier?

2. For 115V output voltage, please recommend what is the suitable Vds rating for SR MOSFET with full-bridge and center tapped full wave rectifier.

3. During the output short condition, would it induce excessive voltage spike on SR FET? Do they need to take this into consideration when picking the SR FET?

4. What is the purpose of output inductor other than filtering? Can they remove output inductor like full-bridge LLC?

Thank you.

Best Regards,

Wei-Hao

  • 0
    TI__Mastermind 25570 points
    Hello Wei-Hao

    The choice of rectifier depends on the output voltage and the current level. For low Vout (12V) the centre tapped secondary with SR is a good choice. For High output voltages (400V for example) a full bridge rectifier with SiC diodes is a better choice. At 115V and 15.6A I think that either a full bridge with either diodes or SR is probably the best solution.

    The voltage rating for the SR or diode depends on the turns-ratio of the transformer. for the Centre tapped configuration the rectifiers will see 2*Ns*Vin_max/Np. For the full bridge configuration the stress will be half this or Ns*Vin_max/Np. Of course this calculation allows no margin for derating or transient conditions. By the way, the equation 85 in the UCC28950 datasheet on page 47 is incorrect - the factor of 2 is missing.

    Voltage stresses on the SRs during output short circuit condition is difficult to predict - it depends on a lot of things which are not related to the controller. For example - the MOSFET driver propagation delay from the CS signal passing the over load limit of 2V on the CS pin until the MOSFETs actually turn off . The 'quality' of the short - how many milliOhms. The PCB track resistances etc. etc.

    The phase shifted full bridge is a buck derived topology so the output filter is part of the basic topology and cannot be removed. One benefit of this is that the ripple current in the output capacitors will be much, much lower in the Phase Shifted Full Bridge than in the FB-LLC (approximately a factor of 9 times lower). This means that significantly less output capacitance is needed.

    Please let me know if you need any m ore information
    Regards
    Colin
  • 0 in reply to Colin Gillmor
    TI__Expert 3260 points
    Hi Colin,

    Thank you for your answers.

    Best Regards,
    Wei-Hao