Dear Team,
Can you please support the following customer question below ?
The design is now in bring up tests validations.
The design is set: to: swFREQ =400KHz, Mode= Diode Emulation , External limiting for the Inductor current MAX pk = 12A (Rsense=5mOhm + Ext voltage offset)
The problem is: AFTER powerup, I am changing the load from Zero to 1A and the controller enters to a latch mode.
Watching after the Various controls Inputs of the controller, NO Fault condition was noticed (as you can see in the attached pictures to this mail)
No current limit was reached,
No UVLO was crossed down,
No SS_pin was pulled down.
I would appreciate if you / TI team can put some light solving it.
In addition Two Questions:
1) how I can configure the design to work in “Bypass Operation” mode
2) how can I control (AT POWER UP) the time between the DG raise to VGS Threshold detection time ? (how the controller detects it?)
Please see below waveforms and schematics.
Best regards,
Nir.
