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UCC28950: UCC28950 synchronization signal setup problem

Lenna Yan
Intellectual 1960 points
Part Number: UCC28950


Hi all,

One customer used UCC28950 to design a power with 48V input, 12V output and maximum output current 35A. Set the clock frequency 400KHz, namely, switch frequency is 200KHz. The plane transformer and inductance are used in this design.Both the primary MOSFET and the rectifier MOSFET adopt TI's CSD19534 and withstand voltage of 100V.

1. Replace the rectifier MOSFET (full wave rectification) with Schottky before joining the synchronous rectification, and strictly deduct ZVS parameters.Due to the maximum current limitation of shottky, the maximum output current is 6A. Under the light load condition, the test result looks stable, the advanced arm is fully realized ZVS, and the lagging arm is not fully realized ZVS.

2. The no-load input current is 20mA under the schottky rectifier condition;The efficiency with 2A load is 86%. Output voltage ripple is less than 1%. The critical output current for CCM and DCM is 3.5A. When the output current reaches to the 4.4 A (wholly go into the CCM), synchronous signal OUTE and OUTF are enabled, secondary side driver is LM5111-1, output is stable.

3. Replace schottke with CSD19534 (two CSD19534 parallel, no RC absorption circuit). When the output current is added to 2.7A, 4 MOSFET of the output rectifier breakdown, and  G,S and D are all short. After recovering the schottky rectifying tube, when the circuit starts up without load, an output voltage can be found, while when the circuit starts up with 0.1A load, output voltage is zero. So there may be some device damaged at the primary side.

UCC28950 synchronization Settings are as follows:

RAEFHI does not install, which means CS and ADELEF open the way;RAEF is set to 0, which is ADELEF pin grounded.We analyze that the sync signal is not related to CS, but do they need to be relevant?The DATASHEET is not clear.Look at the reference design RAEFHI is generally several megohm.

Question: Is the above analysis reasonable? Does RAEFHI have to be installed? Or is there another reason? It's best to give the principle.Thank you

Best regards!

  • 0
    TI__Mastermind 25570 points

    Hello Lenna

    RAEFH does not have to be installed and tying ADELEF to GND is the correct thing to do if you do not want to use the adaptive delays feature on the Synchronous Rectifiers (SR).

    How have you parallel connected the CSD19534 devices ?. At a minimum you will need separate gate drive resistors - one resistor per MOSFET. Paralleled MOSFETs can oscillate at a very high frequency (>100MHz), separate gate resistors and a careful layout with minimum source inductance helps to prevent these oscillations.

    One suggestion would be to run your PSU with only 2 of the 4 SR MOSFETs connected - this avoids the problems associate with parallel operation of MOSFETs.

    It is possible to run the SRs without using the adaptive delay - set the initial SR delay (DELEF) to a low value - it's difficult to say what the correct time should be but choose the resistor at the DELEF pin to set a delay which is 100ns to 200ns longer than the delay set by the resistor at the DELAB pin. This should turn the SRs off after the secondary current is transitioning from one winding to the other but before the current has reached zero or gone negative. You should see some body diode conduction and the duration of the body diode conduction will increase as the load current increases. The adaptive delays (ADELEF) on the SRs increase the delay before the SR is turned off so that the body diode conduction interval is minimised.  Have a look at the plot below.

    Once you can get the SRs running without the adaptive delays I would then add the adaptive delay function and get a first pass solution for the delay time. Then I would add in the paralleled SRs and refine the adaptive delays function.

    Note: if you allow the turn-off delay to be too long then the SR current can go negative - that is, from drain to source - if the SR is turned off with negative current you will see significant voltage spikes on the SR - these can avalanche and destroy the SR. For this reason it is better to initially start with a SR delay which is too short rather than one which is too long.

    Regards

    Colin