Hi Guys
According to the description in the BQ769X0 manual, the time distribution between equalization and sampling is 87.5ms and 12.5ms, respectively, which is fixed and there is no way to change it, but according to my understanding, the sampling line input is RC filtered and the equalization sampling is switched The time should be related to the values of R and C. When the equalization is enabled, the charge stored on C will be consumed. When the sampling is turned on, the capacitor is charged through the 1K resistor, so a certain delay is required. The value of the RC filter circuit in the designed circuit is 1K and 1uF, respectively, as shown in the figure below.
A phenomenon has been found through testing. Once the equalization is enabled, the first string of samples in each sampling group (BQ chip is a string of 5 strings) is abnormal and the sampling are all higher. Is it possible to put two 1uF strings in the first string? Filter capacitor related, if so, then the RC filter value should be how to design.
