TPS2490 - IRF6718

Yes, a 1.2m-ohm current sense resistor is correct.

A spreadsheet design tool exists that can assist on choice of TPS2490 external components. Please give this a try, then if you run into difficult we can help you work thru the details.

http://focus.ti.com/docs/toolsw/folders/print/tps2480-81-90-91-92-93_calc.html

Hi Eric,

Thanks for your feedback.

I went through the spredsheet and got the following results for used IRF6718.

Can give me a hint for the bad SOAt result ?

And makes the outher setting sense for you ?

regards

Carsten

Calculations for power limit control (no external cap on PROG)
Parameter	Description	Value	Units
Vcurrent_trip	Over-current limiting sense threshold voltage	50.000	mV
VIH(EN)	EN UVLO comparator reference voltage	1.350	V
VREF	VREF pin voltage	4.000	V
Vtimer_trip_th	TIMER fault threshold voltage	4.000	V
VPG_th_min	Minimum power-good threshold voltage	0.800	V
Itimer_pullup(max)	TIMER pullup current during fault (max)	34.000	uA
Itimer_pullup(typ)	TIMER pullup current during fault (typical)	25.000	uA
VCC (max)	Maximum system input voltage (magnitude)	12.000	Volts
Cout	Load Capacitance	220.000	uF
Imax	Maximum continuous load current (magnitude)	34.700	A
Ilimit	Current Limit, 20% higher than maximum continuous load current	41.640	A
Rs_cal	Calculated current sense resistor	1.201	m-Ohm
SELECT A SENSE RESISTOR WITH THE CLOSEST AVAILABLE VALUE OF Rs_cal
Rs	Select the closest available value of Rs_cal	1.200	m-Ohm
Ilimit_final	Final current Limit Set Point	41.667	A
CHECK THE NEW Ilimit and SEE IF IT IS IN THE RANGE OF 110% to 130% OF Imax.  IF NOT, RE-SELECT Rs.
VCC_uvlo	Application required input supply under-voltage-lock threshold	10.200	Volts
R1+R2 (max)	Maximum total resistance for the divider -sets Vuvlo	204.000	k-Ohm
R2 (max)	Maximum resistance for the bottom resistor of the divider	27.000	k-Ohm
R2	Select a resistance for R2 that is less than R2(max)	27.000	k-Ohm
R1	Calculate the top resistor value of the divider	177.000	k-Ohm
Eff (min)	Minimum effeciency requirement of hotswap stage	99.500	%
VDSS (min)	FET drain-source voltage rating (minimum)	24.000	V
ID(min)	FET drain-source current rating (minimum)	83.333	A
Rds(on)_max1	FET maximum allowable Rds(on) due to efficiency requirement	0.529	m-Ohm
Rds(on)_max2	FET maximum allowable Rds(on) due to PG threshold	19.200	m-Ohm
Rds(on)_max	FET maximum allowable Rds(on), with 30% tolerance	0.370	m-Ohm
M1	SELECT A FET BASED ON VDSS, ID, and RDS(ON)_max	IRF6718
Tj(max)	FET maximum junction temperature	175.000	°C
TA(max)	Maximum ambient temperature of the application	45.000	°C
RqJC(max)	FET maximum thermal resistance, junction-to-case (J-C)	1.800	°C/W
ZqJC	FET normalized transient thermal impedance, J-C (single pulse). Default=1	0.010
RqJA(max)	FET maximum thermal resistance, junction-to-ambient	12.500	°C/W
Rds(on)_max	FET maximum Rds(on)	0.500	m-Ohm
Tj(operating)	FET junction temperature at maximum application ambient temperature	52.526	°C
Cell turns RED if Tj(operating) > Tj(max); choose another FET and restart
Pfet(lmt)	FET transient power limit	3791.094	Watts
Psupply(lmt)	Maximum supply power limit	500.000	Watts
Plimit_max	Maximum power limit can be set	1666.667	Watts
Plimit	Power limit setpoint; min of Pfet, Psupply or Plimit_max	500.000	Watts
Cell turns RED if Plimit is too low forcing Vprog < 400mV; continue
R3+R4 (max)	Maximum total resistance for resistor divider (R3 + R4)	220.000	k-Ohm
R4 (max)	Maximum resistance for the bottom resistor of the divider	66.000	k-Ohm
R4	Select the bottom resistor of the divider, must < R4(max)	63.000	k-Ohm
R3	Calculate the top resistor value of the resistor divider	147.000	k-Ohm
R3	Select the top resistor of the divider	147.000	k-Ohm
Vprog	Prog pin voltage (typical). Ensure that Vprog > 0.4V	1.200	V
Plim_actual	Actual power limit using actual R3 and R4	500.000	W
Cell turns RED if Vprog is < 0.4V, proceed through T_timer section below
R5	Recommended minimum gate resistor to reduce noise	10.000	Ohm
R6(min)	Minimum PG pull-up resistor	6.000	k-Ohm
R6(max)	Maximum PG pull-up resistor	480.000	k-Ohm
R6	Select the PG pull-up resistor between min and max	10.000	k-Ohm
ton	FET on-time for the capacitive load	0.063	ms
CT(min)	Minimum timing cap with 40% capacitance tolerance	0.001	uF
CT	Select a capacitance that is larger than CT(min)	0.001	uF
T_timer	Typical fault time	0.160	ms
If Vprog is > 0.4V, proceed to SOA section below
SOA derating check
Parameter	Description	Value	Units
MRds(on)_temp	FET Rds(on) multiplier using FET Rds(on) vs. temp curves	1.400
Tj(elevated)	FET elevated max junction temperature	55.536	°C
DFsoa	SOA derating factor	0.796
Vsoa	Power limited Vds: Use Vsoa, T_timer with FET SOA curve to get Isoa	12.000	V
Isoa	Id from FET SOA curve using Vsoa and T_timer	50.000	A
SOAjmax	FET SOA junction power from Vsoa and Isoa at 25C case temperature	600.000	W
SOAt	Derated SOAjmax. Ensure SOAt is greater than Plim_actual	477.857	W
Cell turns RED if SOAt < Plim_actual; a more robust FET or improved heat sink is required
Calculations for dV/dt control (external cap on GATE and no external cap on PROG)
Parameter	Description	Value	Units
Icharge(max)	Choose Icharge less than Plim_actual / VCC(max)	41.667	A
tcharge(min)	Based on Cout, VCC(max), and Icharge	0.063	ms
Qgd	M1 gate-drain charge (from M1 gate charge plot)	14.000	nC
Vgs(th)	M1 gate-threshold voltage (from M1 gate charge plot)	4.500	V
Igate	Typical GATE charge current	22.000	uA
Cg(min)	Using Qgd (install 1k-Ohm resistor in series with Cg)	-2.995	nF
Cg	Select Cg greater than Cg(min)	4.700	nF
tcharge	tcharge using selected Cg	4.261	ms
Icharge	Icharge using selected Cg	0.620	A

Your analysis seems reasonable. We are a bit uncomfortable with this type of MOSFET package. The transient thermal curves represent Z theta J-A for this package while our spreadsheet tool expects Z theta J-C (actual or normalized). You could ask IRF if they could provide curves for Z theta J-C and rerun the tool. I have attached the spreadsheet updated with a seemingly workable solution assuming a normalized Z theta JC of 0.15 (educated guess).

FYI, TI has a line of MOSFETs suitable for this type of application. Several 12V, 40A (50A trip) EVM designs exist which use the same TPS2490 based power limiting hot swap controller (TPS2480EVM and TPS2492EVM). These EVMs use a pair of CSC16401Q5A FETs in parallel for this. You could copy the EVM design and adjust the current sense resistor as required.

http://focus.ti.com/general/docs/lit/getliterature.tsp?literatureNumber=sluu370a&fileType=pdf

I am doing TPS2480 using IRF6718. How do you calculate FET Rds(on) multiplier using FET Rds(on) vs. temp curves? I am not sure how to read the curve to find the multiplier.

These curves are (usually) normalized to 1 at 25C so getting the multiplier is fairly straightforward. For this case, use the FET elevated junction temperature calculated in cell C79 (~92C for the spreadsheet you sent). Then go to figure 7 on pg 4 of the IRF6718 datasheet and use 92C on the X axis to find the multiplier on the RDson curve (~1.25 on the 10V Vgs curve).

Correction:

Use the temperature calculated in cell C47 (cell C79 recalculates elevated junction temperature using the multiplier). So for this case find the multiplier using ~78C (~1.20 vs. 1.25).