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TPS51116 DDR2

joel baylon
Prodigy 120 points
Other Parts Discussed in Thread: TPS51116

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Hi,

I've designed a new board that uses TI's TPS51116 to power the DDR2 SODIMM.

TPS51116 outputs a valid 1.8V VDDQ when no memory module is inserted.

Once i power up the board with a module is inserted, the VDDQ output only goes up to 1V.  I can get to rampup to 1.8V once i probe around the PGOOD, S3, and S5 pins. 

I can see noise like toggling on the PGOOD when the output doesn't reach the proper 1.8V output.

I only have 1 SODIMM. So i don't think i'm overloading the chip, though the module i'm placing is dual rank.  The pins are also all OK as i've tested them to be free from any short.

When VDDQ output is 1V, i can see a different output waveform on the DRVL line as when the output is 1.8V.

Schematic was taken from a Freescale reference design (MPC8349).  Any pointers on where i can look or documents that might help me figure what's wrong would be highly appreciated.

I think the PCB guidelines were met except for the location of the VTT capacitors.  I've placed them near the load rather than the TPS51116 pins.  But i've tried relocating them near the pins but still the problem is there.

Analog is not my strong point and TI's tech support seems to be very busy as i haven't received any acknowledgement from them in the last 2 weeks that i've posted my problem.

Thanks!

Joel

  • 0
    TI__Guru 56805 points

    Joel,

     

    I am not familiar with this reference design, but here are a few things to check:

     

    1) Check to make sure the S3 and S5 pins are in their proper state.  If these pins are floating, noise could be causing the IC to enter and/or exit Sleep Modes.

    2) Check the inductor value.  If the inductor value is too low for the load current, the output could have excessive ripple on it and cause start-up problems.

    3) Check the current limit programming.  The TPS51116 can be configured to use a resistor between GND and CS or the Rdson of the low-side FET, with a resistor from CS to V5FILT

    4) Check the connection of VTTSNS to the VTT capacitors.  VTTSNS should be conected to the VTT terminal of the VTT bypass capacitors and not directly to the VTT pin.  Even a few milliohms of extra ESR between the VTT capacitors and VTTSNS can cause a low voltage, very high frequency oscillation on VTT that draws a lot of current from VLDOIN and can trigger current limit.

    5) Check to make sure there is a pull-up on PGOOD.  The TPS51116 uses PGOOD to change the current limit value during start-up, if PGOOD does not have an external pull-up, the current limit function may not properly trigger.

  • 0 in reply to Peter James Miller
    Prodigy 120 points

    Hi Peter,

     

    1.  S3 and S5 are both pulled up to 5V.

    2. Inductor value was taken from the reference design which is 1uH.  Reference design has 2 SODIMM connectors so i figured it's safest to just use the same inductor.

    3. Not sure about this.  The circuit i'm using is based on the D-CAP mode.

    4. I'll look into this.

    5. I didn't place any PGOOD pull up resistor on the original board design as i think it's optional and i didn't realize i'll have use for it (now i know!).  I'm only placing the PU resistor on top of the pin and wiring it to 5V.

    I have 2 boards that are working at the same level.  I've placed a snubber circuit (recommended from the datasheet) between LL and PGND and it somehow fixed the issue on 1 board.  I used to see it still drop to about 1.4V, but so far this week, it has been consistent and i can get 1.8V after power up.   But this is not the case for the other board as i've done the same and it's still dropping to 1V after power up.

    Thanks again!  I'll look into your other suggestions tomorrow.

     

    Regards,

    Joel

  • 0 in reply to joel baylon
    TI__Guru 56805 points

    Joel,

    Please keep me informed about your progress.

  • 0 in reply to Peter James Miller
    Prodigy 120 points

    Hi Peter,

    I'm still not sure about item 3.  I guess this doesn't apply when DCAP mode is used?

    On item 4,  VTTSNS is connected to the midpoint of the VTT island and not directly to the VTT pin. What confuses me on the PCB implementation is the placement of the VTT output capacitor.  Below are statements taken from the TPS51116 datasheet

    · The output capacitor for VTT should be placed close to the pin with short and wide connection in order to
    avoid additional ESR and/or ESL of the trace.
    · VTTSNS should be connected to the positive node of VTT output capacitor(s) as a separate trace from the
    high current power line and is strongly recommended to avoid additional ESR and/or ESL. If it is needed to
    sense the voltage of the point of the load, it is recommended to attach the output capacitor(s) at that point.
    Also, it is recommended to minimize any additional ESR and/or ESL of ground trace between GND pin and
    the output capacitor(s).

    I've placed 2 10uF ceramic capacitor at the point of the load.  Now, i've tried relocating 1 of the capacitor near the VTT pin and leaving the other 1 at the point of load.  The mod seems to work OK as i haven't seen any dip on the VDDQ or VTT output of the TPS51116.  I'm now going to try it on my 2nd board and see how it goes.

     

    Thanks,

    Joel

     

  • 0 in reply to joel baylon
    TI__Guru 56805 points

    Joel,

    First, Current Limit functionality and programing is independant of the control technique selected.  D-CAP mode control can use Rdson current limit (resistor from V5IN to CS) or resistive current limit (CS connected to the junction of a series current sense resistor and the source of the low-side FET)  Current limit maintains the LDRV "ON" time until the voltage drop across the current sense element (low-side FET or current sense resistor) falls below the threshold.

    Second, if VTTSNS is connected to the VTT island at the mid-point of the island, the VTT bypass capacitors should be located at the midpoint of the island for stability.  If this causes an undesirable drop in the VTT voltage at the end-points of the island due to distribution losses, it can be desirable to add smaller bypass capacitors (1.0 or 2.2uF) at the end-points or even use 3x 10uF capacitors with one at the mid-point and 1 each at the two end-points.  What is critical to the stability is the impedance from the VTTSNS pin through the bypass capacitors and back to the GND of the TPS51116 controller as this is the loop seen by the VTT regulation circuit.

    The configuration you describe with 1 10uF at the IC and 1 10uF at the sense point is non-optimal, but likely effective if there are other, higher frequency bypass capacitors along the VTT island (such as a collection of 0.1uF local bypass capacitors) to reduce the impedance seen by the VTTSNS node.

  • 0 in reply to Peter James Miller
    Prodigy 120 points

    Hi Peter,

    I've just noticed something when i was trying to bring the 2nd board to the same level as the first.  It looks like i'm not really getting 1.8V out but instead only 1.6V!

    There are 25 0.1uF ceramic capacitors that are situated near the pull resistors for the DDR2 control lines.  I've also placed 3 4.7uF tantalum caps and 3 100uF tantalum caps along the corners of the VTT island.  These capacitors are not modifications on the board and are already there from the original design.  The caps are all low ESR versions.  I'm just not sure how low.

    I'll try to digest first the Current Limit info you've mentioned.

    Thanks,

    Joel

  • 0 in reply to joel baylon
    Prodigy 120 points

    Hi Peter,

    Disregard the statement where i said i'm reading 1.6V.  It's only the case of the 2nd board that i'm working on.  And it's not the case on the first working board as it still powers up to 1.8V.

    Still, on the second board that powers up to 1.8V when no module is installed, and powers up to about 1.6V when a memory module is installed, playing around the PGOOD and S3, S5 pins can ramp up the output to a stable 1.8V.

    Still digesting the Current limit stuff u mentioned.

    Thanks,

    Joel

  • 0 in reply to joel baylon
    TI__Guru 56805 points

    Joel,

     

    Look at your schematic.  On the TPS51116 controller, find the CS pin.  What is connected to CS?

     

    This pin should either be:

    Connected to the junction of the source of the low-side FET and a current sense resistor to PGND. 

        In this configuration the current limit is set by the voltage drop across the current sense resistor during the low-side FET ON time.  The drop across the sense resistor is compared to a fixed threshold (20-40mV when PGOOD is low and 50-70mV when PGOOD is high)  To limit the inductor current, the low-side FET is forced ON until the current in the sense resistor falls below this threshold, extending the OFF time and reducing the output voltage.

    Connected to a resistor to V5IN

        In this configuration the current limit is set by the voltage drop across the CS to V5IN resistor compared to the voltage drop across the low-side FET.  The low-side FET is again held ON until PGND - LL < V5IN-CS  (The voltage drop across the low-side FET is less than the voltage drop across the CS to V5IN resistor)  This extends the OFF time and reduces the ouptut voltage.

        The voltage drop across the CS to V5IN resistor is set by an internal current source (4-6uA when PGOOD is low and 9-11uA when PGOOD is high) 

     

    Since pulling up on PGOOD allowed start-up, I suspect that your current limit is set too low to support 1.8V when the memory is installed and PGOOD is low.

  • 0 in reply to Peter James Miller
    Prodigy 120 points

    Hi again Peter,

    CS is connected to V5IN via 5.1K.  The 5.1K value was taken from the TPS51116 datasheet and also from the reference schematic from Freescale.  I am reading around 20~30mV when the output of the TPS51116 is below 1.8V.  When the output is OK at 1.8V, i am reading a value of 50~60mV.  I think that 60mV is the expected value as that is what i've seen on the datasheet.  Would it make sense if i reduce the resistor as long as i can get the Vrtrip within the 150mV limit?

    I am also currently looking at one of your response to a forum post (TPS51116 VTT singal oscillating).   The capacitors i'm using for Vtt is from Panasonic and i can't find the actual ESR value as it's not mentioned on the datasheet (only LOW ESR).  I'll try to find this one out.  I think i'll also try the 1000pF/1k LPF and see how it works on the 2nd board.

    Thanks Peter!

    Regards,

    Joel

     

  • 0 in reply to joel baylon
    TI__Guru 56805 points

    Joel,

     

    CS is connected to V5IN via 5.1K.  The 5.1K value was taken from the TPS51116 datasheet and also from the reference schematic from Freescale. 

    Check the Rdson of your low-side MOSFET.  This is being used as the current sense element.  The current limit during start-up will me 20-30mV / Rdson.  For a 5mOhm low-side FET, this means a current limit of 4-6A but if you're using a 10mOhm MOSFET the current limit might only be 2-3A.

    I am reading around 20~30mV when the output of the TPS51116 is below 1.8V. 

    This is consistant with the controllers current limit programming current when PGOOD is low.

     When the output is OK at 1.8V, i am reading a value of 50~60mV.

    This is also consistant with the current limit programming current when PGOOD is high.

    Would it make sense if i reduce the resistor as long as i can get the Vrtrip within the 150mV limit?

    Yes, but you would INCREASE the resistor value to get a higher Vtrip voltage.  You need to adjust your resistor with the Rdson of your low-side FET.  try increasing it to 7.5kOhms and see if your start-up problems go away.

    I am also currently looking at one of your response to a forum post (TPS51116 VTT singal oscillating).   The capacitors i'm using for Vtt is from Panasonic and i can't find the actual ESR value as it's not mentioned on the datasheet (only LOW ESR).  I'll try to find this one out.  I think i'll also try the 1000pF/1k LPF and see how it works on the 2nd board.

    If it's the panasonic 0805 10uF capacitor, you should be ok, if you've followed the layout guide lines.  If it's a larger package device (1206 or 1210) the ESL is a little highter and it could be causing a stability issue.  Try using an oscilloscope probe directly across the capactor and measuring the AC ripple voltage.  If it is unstable, it typically oscillates 5-10mV amplitude at 700kHz - 5MHz.  Even a small oscillation as very high frequency can draw a huge average current.  There should be almost no ripple at all on VTT when no load is applied. 

  • 0 in reply to Peter James Miller
    Prodigy 120 points

    Hi Peter,

    - I'm using a 5mOhm low-side FET (IRF7832).

    - I'll  try increasing it 7.5K.

    - it's the 0603 version.

    i'll try the other stuff out and see how it goes. 

    Thanks again!

    Regards,

    Joel

  • 0 in reply to Peter James Miller
    Prodigy 120 points

    Hi Peter,

    Not much luck on the 7.5K.  One thing i noticed though on the PGOOD output, what i thought was due to scope probe looks to be like momentary pulses on the PGOOD.  I initially thought i was not getting good contact on the pins but it looks like the PGOOD is pulsing.  And if i wait for a while, it goes high and the 1.8V output is OK.  At powerup though, it's still around 1.6V, and sometime around 1V for this 2nd board.

    I can see some ripply on the VDDQ line although i think it matters on where i probe the signal.  If i do it on the testpoint, there a substantial ripple which is near 100mv pk-pk.  But not that much if i do it near the connector.

    Thanks,

    Joel

  • 0 in reply to joel baylon
    Prodigy 120 points

    4606.LL_route.pdf

    Hi again Peter,

    I'm still stuck on this issue.  I now have 3 boards powering up the same way (with 1 going up to 1.8V but still cause problems in powering up/initializing the DDR2 SODIMMs plugged to the board). 

    I rechecked the layout considerations  and i was just wondering maybe you have some input on the layout done on pin 18 (LL).  From the datasheet, it just states, LL should be as short and wide as possible. 

    I've attached a pdf file (hope u can see it) that highlights the LL route.  Total length of the net is about 28mm. Width is 0.381mm.  Do you think this can cause the problems i'm having?

    Thanks,

    Joel