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TPS65218: DCDC1 and DCDC2 PGood Off Delay Time Question

Part Number: TPS65218

Hello Team,

 

We are testing TPS65218 in the system and have some questions. May I have your help comment on it?

When PGood changes from high to low, based on datasheet Figure 5-8, DCDC2 should turn low before DCDC1. DCDC2 delay time is DLY9. DCDC1 delay time is DLY9+DLY8. But we measured the waveform and saw DCDC1 drops faster than DCDC2. Please see the picture in bottom for illustration.

 TPS65218 Question.pdf

Is this measurement method problem causing DCDC1 seems drop faster than DCDC2? 

Thank you.

Regards,

Ting

  • Ting,

    Are you using TPS65218D0 or TPS65218 (-B1 or -B101 version)?
  • Hello Brian,

    It is TPS65218. Could u let me know if it is more likely to be measurement issue or application issue that could cause the device to not function? Thank you.
    Regards,
    Ting
  • Ting,

    You need to monitor the IN_BIAS and INT_LDO pins also and determine if they are below 2.5V

    It will also help to read Sections "5.3.1.6 Internal LDO (INT_LDO)" to determine if the TPS65218 is attempting to go through the power-down sequence correctly or if an instantaneous power-down is occurring.

    If the back-up battery path (BU) is also used, section "5.3.1.12 Battery-Backup Supply Power-Path" is also important.

    It appears to me that an Instantaneous shutdown is occurring, based on the diagram you shared.
    This means DLY8 cannot be observed and the RDIS discharge resistor of ~250 Ohms would be enabled on both DCDC1 and DCDC2 at the same time.

    If the internal RDIS resistors are mismatched or there is a difference in the external capacitance or load on DCDC1 vs. DCDC2, this would explain the reason the curves are not identical.