Perhaps software engineers should not be put on hardware design projects. I am at my wits' end with this thing.
Here is what I am trying to do...
I have 4 TLC5941s cascaded to drive a dot-matrix LED display. The data for each row of the display is shifted into the TLC5941s, latched, and then the row (row N) is turned on. While it is on, the data for the next row (row N+1) is shifted in. Then I do BLANK and XLAT to latch the data, and simultaneously power off row N and power up row N+1. So far, so good, right?
The problem is getting the MPU to shift the bits into the TLC5941 fast enough to meet the timing requirements. The display has 25 rows. If I refresh the display at a rate of 100Hz, that means I need to shift in a row worth of data at 2500Hz (so I have 400 microseconds per row to shift in the data). With 4 TLC5941s, I have to shift in 192 * 4 = 768 bits (plus time for BLANK and XLAT signals) in 400 microseconds. This means I have to shift a bit in about every 520.833ns, for a shift rate of 1.920MHz.
My questions are:
1. Is the above timing analysis correct?
2. Do I need 772 (768 + 4) SCLK pulses per row, or 769 (192 bits * 4 PWM data, plus one more clock pulse to turn XLAT on and off)? The timing on the data sheet confuses me. It shows a 193rd clock pulse after the 192 bits of PWM data have been shifted into the TLC5941. With four 5941s cascaded, they will all latch from the same XLAT pulse. Is there just one extra clock pulse at the end of the entire row of cascaded 5941s (769 SCLK pulses) or one for each cascaded chip (772 SCLK pulses)?
3. I was planning to use the SPI port from a Freescale MC9S08GB60A for this, and use the SPI's clock signal to clock the 5941 SCLK and GSCLK signals. Is this reasonable, or should I use a GPIO pin, and bit bang my own clock signals from another GPIO pin? Would it be easier to toss out the Freescale chip and use a different MPU?
I know that someone more knowledgeable than I can answer this. Thanks in advance for any help you can provide!
