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UCC28950: SLUSA16D

SAMRAT PUJARI
Intellectual 730 points
Part Number: UCC28950

Hello

In SLUSA16D

Output ripple voltage VIN = 370 VDC to 410 VDC, IOUT= 5 A to 50 A 200 mV is one of the design specification but it is not used anywhere in design calculations? how it is met?

thanks

samrat

  • 0
    TI__Mastermind 25570 points

    Hi Samrat

    You are right, the ripple is not calculated directly however a first pass estimate would go something like this - using the values in the data sheet example.

    Peak to peak output inductor ripple current is 10A.

    Switching frequency is 100kHz - the output inductor sees twice this and I'll assume a worst case duty cycle of 90%

    The output capacitor has been sized according to a hold up time and transient requirements and chosen to be 5600uF with an ESR requirement of 12mOhm.

    The actual capacitor selected to meet these requirements is 7500uF and 6.2mOhm.

    So - and to a first approximation.

    The inductor ripple current flows in the output capacitor where it causes a voltage of 10A * 6.2mOhm = 62mVpeak to peak.

    We also need to look at the voltage change on the capacitance due to the inductor ripple current:  dV = (i * dt) / C or dV = (10 * 5us * 90%) / 7500uF = 6mV

    These voltages (to a first approximation) will add so the peak to peak ripple should be about 68mV - easily meeting the specification.

    It would be straightforward to model this system and confirm these results.

    BUT !!!

    The above calculation will give you the voltage ripple at the switching frequency to a reasonable level of accuracy however it will not give you any indication of the peak to peak noise due to switching events as the various MOSFETs and SRs are turned on and off. These high frequency noise spikes are close to impossible to model accurately - they are a strong function of the component parasitics (Qrr for example) and of PCB layout. Normally one adds some high quality ceramic capacitors at the PSU output terminals to filter this noise but it is important to have a good PCB layout with minimum unclamped stray inductance in the loops where current is switched on and off.

    Regards

    Colin