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TPS53667: Pattern layout

K. Sasaki14
Guru 10200 points
Part Number: TPS53667
Other Parts Discussed in Thread: TPS53688

Can we put TPS53667 on back side layer of under power inductor and switching pattern because we want to reduce circuit area?

We have any consider about noise, especially PWM, CSP and feedback line. If it is possible, please let me know the point which we should care about layout pattern.

And datasheet has description about "Current Sensing line" layout guideline.
According to that, CSP line should run in the VREF plane. Why is this required? What concern do you have if CSP line is not in the VREF plane or there is no VREF plane?

Best Regards,
Kohei Sasaki

  • 0
    TI__Mastermind 49450 points

    Hi Kohei,

    We recommend placing TPS53667 on the top layer and keep>800mil away from the switching node of power stages to avoid switching noise coupling. If you put the TPS53688 directly underneath the power inductors and switching nodes, you may hurt the performance with heavy jitter, more noise and inaccurate Iout reading etc. For the layout, you need pay more attention to PWMx, CSPx and feedback traces routing. Run those traces in the signal layers and keep >60mil clearance from any 12Vin vias, 12Vin coppers and switching nodes vias. Regarding CSPx routing, because VREF from controller side must be connected to REFIN pin of each power stages since VREF is the current sense reference voltage for current sense amplifier of power stage. To reject the interference, CSPx and VREF must be routed as either differential pairs all the way from controller to power stages or CSPx embeds inside the VREF copper plane (generated a VREF copper plane). If it is hard to have a VREF copper from controller to power stage, you can generate a small copper plane near controller side and route CSPx /VREF as a differential pair from controller to power stages.

    If you are still not clear, please email me directly, I can show you the CSPx routing example. nancy_zhang@ti.com

    Thanks,

    Nancy