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TPS53667: layout guideline of current sensing lines

Yuto Sakai
Mastermind 6100 points
Part Number: TPS53667

Hi,

I have a question about the layout guidelines of datasheet P110.
Why does current sensing lines recommend wiring with VREF layer?

Best regards,
Yuto Sakai

  • 0
    TI__Mastermind 49450 points
    Hi Yuto,

    Regarding CSPx routing, because VREF from controller side must be connected to REFIN pin of each power stages since VREF is the current sense reference voltage for current sense amplifier of power stage. To reject the interference, CSPx and VREF must be routed as either differential pairs all the way from controller to power stages or CSPx embeds inside the VREF copper plane (generated a VREF copper plane). If it is hard to have a VREF copper from controller to power stage, you can generate a small copper plane near controller side and route CSPx /VREF as a differential pair from controller to power stages.
    If you are still not clear, please email me directly, I can show you the CSPx routing example. nancy_zhang@ti.com

    Thanks,
    Nancy