TPS65218: Does TI have power solution or reference design with Lattice LFE5UM-45F-BG381

Jason,

Where do these load current requirements come from? Since this is an FPGA, usually there is a "power estimator" tool that the customer uses to enter their usage of the FPGA clocking speed/logic cells to determine how much current is required by each rail. It seems a little suspicious that each rail requires exactly 1.5A because the current needs of an FPGA can fluctuate wildly depending on usage.

With a 12V input, you will need a pre-regulator to use a PMIC.

The TPS65218D0 is a good choice because the total # of rails is similar to your requirement, but the TPS65218D0 will require custom OTP if any output voltages and sequencing requirements are different between Lattice and AM43x. The default output of DCDC1 and DCDC2 on TPS65218D0 are both 1.1V so this difference alone means it will need custom OTP.

My suggestion would be to check the current requirements and see if any two of them can be reduced to 1.2A and 1.0A

If this is possible, use the TPS54424 as a pre-regulator to go from 12V to 3.3V at 4A and supply the 3.3V I/O rail from this voltage directly.
Then you can use the TPS65023B, which has 3 externally configurable DC-DC converters, to generate 2.5V, 1.5V, and 1.1V from the 3.3V output of the TPS54424.

For the TPS65023B: DCDC1 can supply a load of up to 1.7A, DCDC2 can supply a load of up to 1.2A, and DCDC3 can supply a load of up to 1.0A