Hello Vishal,

Thank you for interest in the UCC28730 controller. The PMP40025 reference design is definitely correct. It has a test report with performance data to prove it.

I believe the Webench limitation is based on application simplicity. The UCC24650 VDD and WAKE maximum voltage ratings impose practical limits for the output voltage - when configured in the usual output circuit arrangement shown in the datasheet. Webench is not sophisticated enough to expand on special design tricks to accommodate these limitations to all possible applications.

The PMP40025 design implements voltage-limiting techniques to adapt the UCC24650 to be used in a higher-voltage application than its ratings would imply. The UCC28730 controller makes no limits on the allowable output voltage since the transformer scales the voltages to suitable levels on the primary side.

Please do use the reference design as a guide for your application.

Regards,
Ulrich

Hello Vishal,

I recommend that you do please go through the Webench design exercise in order to get an idea of the parameters and sizing of the transformer that you will need to find. Webench will generate a transformer design suited to the application and give you the specs to build or procure it.

Off-the-shelf (OTS) transformers will probably not have all of the minimum requirements for your application, or may fit everything except one aspect (power capability, output voltage, etc.) may fall short. Most likely, your OTS choice will have to be over-designed in order to meet your needs.

Then, it is a matter of sorting through the available products to find one that is closest to the Webench design, without being under-designed in some aspect. I tried to do some searching for a 48-W flyback transformer for 36V-75V input range and I am appalled at how poorly both Digikey and Mouser characterize their transformer products. I don't know how anyone can find what they are looking for based on the search criteria available. Most of those I found in the 36-72V range are intended for low-voltage lower power POE applications in the forward mode.

Unfortunately, I think it would be a matter of filtering the choices by eliminating all transformers that definitely are not what you need, then painstakingly examining each remaining datasheet to see if the parameters meet or exceed what you need from Webench.
An alternative is to select a few major sources (Wurth, Bourns, etc.) and go to their websites to search their offerings first and select some that exceeds your needs, then see if any of those are available from a distributor.

Another alternative is to find a transformer that has all of the winding voltages correct, but may be under-powered, and parallel 2 or more of them to reach your 48-W target. I hope this helps you.

Regards,
Ulrich

Hello Vishal,

I will answer your questions first, then explain the major deviations of the PMP40025 design compared to the datasheet example design.

R14 should be 1K as shown in the schematic diagram, not as listed in the BOM. I believe that the person who drew the schematic originally used a 100K part as a convenient place-holder to get the connections down for pcb layout. Later the design was refined and the true value (1K) was edited into the value display, but the manufacturer’s part number was not changed. The BOM is extracted from the schematic by pulling the part numbers, hence the wrong value is listed in the BOM.

C11 and C13 can both use the same voltage rating of 50V or higher. C13 will have about 38V impressed across it (I’ll explain later). C10 needs a voltage rating > 300V due to the worst-case peak voltage across D6. All three could be rated for >300V, of course, but I think the cost for a 500-V cap is higher than that of a 50-V cap, so it makes more sense to me to choose different voltage ratings where appropriate.

This PMP40025 reference design contains three major deviations from the typical flyback implementation shown in Figure 23 the UCC28730 datasheet:
1. It has a linear regulator on the VDD node of the UCC28730,
2. It has a totem-pole buffer on the DRV output of the UCC28730,
3. It has additional components around the UCC24650 “wake-up” IC.

(The reference design also shows the MOSFET voltage clamp network D3, R20-22, C14. Such a network is typical but it was left out of Figure 23 to avoid clutter.)

The VDD regulator is used to reduce the AUX winding voltage to about 11V at VDD. The transformer used in PMP40025 (Wurth Electronik 750343192) has a 3:1 turns ratio from SEC to AUX, so 48V output voltage reflects to ~16V at AUX. I do not know why the PMP designers decided to regulate this 16V down to 11V, perhaps to reduce stand-by power, but I don’t think the regulator sub-circuit is really necessary. VDD can also be lowered by adjusting the turns ratio. I recommend to assume that you do NOT need the regulator (R4, R17, Q3, D8, D5) special circumstances force you into having one.

The totem-pole gate-drive buffer is added to boost the turn-on and turn-off drive of the primary MOSFET. For this 48-W design, the engineer(s) chose a MOSFET with relatively high input capacitance (Ciss) and determined that the drive capability of the IC itself was insufficient to switch the MOSFET on and off quickly enough. Q2 and Q4 increase the on/off drive currents, and C12 provides local decoupling of the current peaks. I recommend that Q2 collector and the bottom of C12 to be connected to Q1 source pin rather than PGND, to keep the higher peak currents out of the R11, R12 and PGND path. For MOSFETs with lower Ciss, this totem-pole network should not be necessary.

The “extra” components around the UCC24650 device ARE necessary in this design because of the 48-V output level. The UCC24650 has maximum voltage ratings of 30V for its VDD and 230V for the WAKE pin. To perform its function (wake up the UCC28730 when a load-step occurs during stand-by conditions) it monitors VDD for a 3% drop in voltage and pulses the WAKE output to send a signal to the UCC28730 VS input by way of the SEC and AUX windings. To adapt it to the 48-V output, a divider network is added to VDD to divide down the output to be within the VDD operating range. To minimize stand-by bias current, R2 and R6 are chosen to achieve about ~10V at VDD. The UCC24650 draws about 45uA at 10V, so total draw on the 48-V output is ~71uA or so. C11 is just a noise filter, but not too big to suppress response to drops in VDD. C13 and R19 improve the detection response to load-step voltage drops on 48 V. The PRI to SEC turns ratio is 5:3, so ~400V bulk voltage during the MOSFET on-time reflects to 240V across the SEC winding. That plus the 48V output plus any leakage inductance spike result a voltage exceeding 288V across the output diode D6 and would be at the WAKE pin. However, 180-V Zener D7 is used to clamp this peak voltage to be comfortably within the maximum rating of WAKE. R14 (at 1K) limits the current into D7. (This peak voltage is also why snubber cap C10 needs a voltage rating > 300V.)

I hope I have explained the significant differences between the typical application and this specific PMP design, and why they were made. Unfortunately, there is no other documentation of the PMP40025 concerning the specific design procedure and reasoning for the design choices, so these represent my best interpretations.

Regards,
Ulrich