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UCC28780: Unrealistic Coss allows Mathcad formula to work?

Gerrit Barrere
Expert 1245 points
Part Number: UCC28780

I'm using the Mathcad documents from sluc644.  In the "Neutron..." worksheet there is a test to make sure the 40 ns delay T.DPWML_H (plus driver delays) is greater than the actual circuit rise time at the switching node (T.rise_max).  The test works fine in the original worksheet, but only because the calculation for C.sw_T (total switch node capacitance) uses a fixed value of 40 pF for C.oss_Q_T (the time-based Coss for the primary switch FET).

I can't find any FETs, GaN or Si, which have this low a time-based Coss.  Typical GaN FETs seem to run more like 200 - 300 pF, and that causes the T.DPWML_H test to fail.  It is suspicious that the C.oss_Q_T in the worksheet is fixed at 40 pF rather than being voltage-dependent.  It's like someone stuck 40 pF in there to make the formula work.  This affects other calculations too.

To get around this should I run the UCC28780 with SET = 5V to select a Si switch even though I'm using GaN?  Will that provide enough delay on T.DPWML_H and not cause other problems?

Thanks for any help.

  • 0
    TI__Mastermind 40580 points
    Hello Gerrit,

    You are right to question this fixed value. There should be a voltage-dependent equation there, similar to that for the Secondary SR MOSFET C.oss_SR_T(Vin,N,Vo) (a power-based curve-fit approximation). The main difference, aside from the numerical values, is that the numerator would be (Vin+N*Vo) instead of (Vin/N + Vo) since this Co(tr) is of a MOSFET on the primary side.

    The fixed 40-pF value was placed there at the last minute before publication of the worksheets in response to concern over revealing 2nd-party proprietary data not publically available. We were (and still are) working with GaN MOSFETs that do indeed exhibit significantly lower Co(tr) values than the 200-300pF that you are quoting. Actually, the Co(tr) of each Fet ranged from 72~47pF over the bulk voltage range of 100~375V. In this worksheet we assumed (because that was the case at the time) that the upper and lower MOSFETS were the same device. So the 40-pF substitute number is a bit understated, but we expected that the worksheet user would replace this with values from the actual Fets being modeled. The other Fet-related parameter values were also “fudged” a bit to obscure any correlation to the real device that we were using.

    Perhaps you are evaluating GaN Fets much larger in size than the ones we worked with, for a much higher power application. If that is the case, I think I agree with you to connect SET to REF (= 5V) to accommodate the additional rise time needed with the larger Co(tr). SET=5V timing adjustments are intended to accommodate slower Si-based MOSFETs. SET adjusts 2 timing parameters: the delay to turn on the upper Fet (QH) after the lower Fet (QL) turns off, and the proper moment to turn on QL.
    When SET = 0V, QH turns on 40ns after QL turns off, and QL turns on when Vsws falls below ~4V.
    When SET = 5V, QH turns on 40ns after VS rises >0V, and QL turns on when Vsws falls below ~9V.

    An alternative to setting SET =5V for large, high-Coss GaN Fets could be to introduce a small R-C delay into the PWMH signal to the QH driver.

    Thank you for pointing out this limitation of the worksheet. I’ll add it to the list of improvements that we need to make.

    Regards,
    Ulrich
  • 0 in reply to Ulrich Goerke
    Expert 1245 points
    Hello Ulrich,

    I sure hope they pay you well there at TI -- you're a gold mine!

    Your answer is excellent and complete, as usual. Interesting you should mention the proprietary devices -- I tried to get data sheets for the Navitas GaN FETs used in the EVM for this IC and was told they are proprietary, and currently Navitas is dedicating their production to an OEM. I need higher voltage than the 650 V normally used for global AC supplies, and the Transphorm 900 V GaN FET is about all I can find. Its C.OSS_T at my operating voltage is 230 pF. I scanned a few other GaN FETs at DigiKey (which don't meet my voltage requirements) and saw that their data sheet C.oss curves looked about the same, also. I guess some mfrs are able to bring that down significantly though.

    Thank you for the tips on circuit adjustment for these higher C.oss GaN FETs. I can certainly make something like that work.

    Best regards,
    Gerrit