Hi Sir,
My customer check the SMbus Timing at falling edge, the test result are lower than specification at SDA and SCL. Could you help to check below questions? Thanks.
Q1: Is there any specific reason to define the minimum requirement for falling edge in the fast mode?
Q2: Is there any thought on how to solve the problem of the clock and data edge failing?
In below data is following (5) requirement.
(5) Rise and fall time are defined with TR = ( VILMAX – 0.15) to (VIHMIN + 0.15) and TF = 0.9 VDD to (VILMAX – 0.15).
