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UCC27517A: Driving MOSFET switching unclamped inductive load

Eric Bretscher
Prodigy 80 points
Part Number: UCC27517A
Other Parts Discussed in Thread: UCC27517

In a low-side MOSFET switching application with an inductive load, is there a requirement to protect the gate / gate driver from transients coming back through the MOSFET drain-gate capacitance, or is the impedance of the driver low enough throughout the switching cycle to keep the voltage on the output of the driver within specs?

  • 0
    TI__Genius 12990 points

    Hi Eric,

    Thanks for asking this question, and welcome to e2e! Im an apps eng with this device, I hope to help you out.

    Switching an inductive load at high speeds and sharp edges, for example in a low side configuration can create a large voltage spike on the drain of the NMOS because of the inductor kicking back the magnetic field to bring the load current to zero.This makes drain-source high dv/dt during switching transitions an issue. If in a bridge configuration, the high dv/dt happens right when reverse recovery of the free wheeling diode happens which can further excite the issue. In some instances the FET clamps the inductive load while experiencing avalanche breakdown and degrades the ruggedness of the FET by exceeding temp limits.

    We are looking at the potential ringing on the gate, miller turn on effect or FET/driver damage exceeding Vds limits. A decrease in gate voltage makes a rise in drain potential and a drain to gate current of C_gd*dVds/dt all during the miller plateau region. Since dC=dQ/dV and the drain voltage changes are large, the drain capacitance can change from small to large depending on VIN. The larger the load and switching times, the larger the dv/dt. As an example, with a 1uH inductor and switch time of 1ns and load current of 1A, Ldi/dt says theres a 1000V kickback. Of course increasing dt to 100ns will bring this kickback down to only 10V.

    If all this is accounted for the drive impedance wont have any affect because the miller turn on voltage comes from Cgd current through the larger gate to source resistor during the transition. If the gate to source resistor is not there then the gate resistor makes the voltage rise from the GND pin during driver turn off. Miller turn on can be avoided by adding a gate resistor or capacitor to limit rise times, Avalanche Breakdown can be avoided by choosing a larger FET. Check out this app note on how to select the optimal gate resistor to help with ringing:

     Hope this helps, please follow up if not clear. Do you have any questions about 517A? what topology do you have and why cant you clamp?

    Thanks,

  • 0 in reply to Jeffrey Mueller
    Prodigy 80 points
    Hello Jeff,
     
    Yes, you are touching on all of the issues involved. The topology consists of two FETs driving opposed low impedance primary windings on a transformer at about 40kHz. Unclamped is the worst case, in reality VDS is clamped using 75V Zeners and the FETs are good for VDS=100V. The drain voltage rises much higher than the 14V supply upon gate turn off of course. While the maximum voltage is clamped, dV/dt remains relatively high.
     
    My question had to do with the effect of Cgd indeed from the FET driver point of view. When the gate is switched to ground by the driver and the FET turns off, the drain voltage spikes, Cgd increases and a current flows from the gate through the FET driver and to ground. The voltage rise at the gate can cause a Miller turn on. My question was about this gate voltage becoming high enough to damage the FET driver (it could also damage the FET by exceeding VGSmax of course). This voltage must depend on this current as well as the gate resistor and the impedance of the FET driver discharging the gate.
     
    Until now, I have clamped VGS using a Zener as well as a Schottky to VDD to control this risk and protect both the UCC27517 and the FET. Miller turn on shouldn’t be occurring and application schematics never show such an arrangement, so in hindsight I thought it may have been overly conservative. The answer seems to be that if dV/dt is acceptable at the drain, protecting the gate and driver this way is unnecessary.
     
    Thanks for taking the time to discuss the subject.
     
    Eric