Can we put capacitor on the GATE pin for reducing inrush and Vout slew rate control?
Please let me know if you have any concern.
I think this is no problem as a device operation, and it depends on application.
I think concern is the timing of FET off. We should use external dV/dt circuit in App note "SLVA673A" if there is any problem about turn-off control.
Is the gate capacitor no problem if there is no concern as an application?
Best Regards,
Kohei Sasaki