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Original question:

TPS65910: Possibility of retaining VDIG1 register contents between power failures

TPS65910: Possibility of retaining VDIG1 register contents between power failures

Srikanth Vemula
Prodigy 130 points
Part Number: TPS65910

Hi,

As suggested in my previous post,I'm writing the VDIG1 register after power on through I2C using 100KHz clock. After write if I perform read operation immediately, it is not happening. Please let me know if you have faced this kind of issue. Any delay need to be provided between consecutive write and read to the same register?

Regards,

Srikanth Vemula.

  • 0
    TI__Genius 9380 points
    Srikanth,
    I am not aware of a timing issue. I have forwarded your question to a product specialist, just in case they are aware of something in the I2C routine. You should hear from someone soon.
  • 0
    TI__Mastermind 30280 points
    An I2C Write sequence to a single register consists of 3 bytes: Slave Address with LSB = 0, Register Address, Data.

    An I2C Read sequence to a single register consists of 4 bytes: Slave Address with LSB = 0, Register Address, Slave Address with LSB = 1, Data.

    So an I2C Read is actually a Write command followed later by a Read command.

    If you are writing data to a single register and then reading back that same data, then there must be at least 7 bytes of data. You cannot perform a Write followed immediately by a Read with 5 bytes of data, which is what it sounds like you have explained.

    For further analysis, I would need to see a scope shot or data log of the issue occurring.
  • 0 in reply to Brian Berner
    Prodigy 130 points

    Hi,

    Thanks for your response. 

    I sorted out the issue. It's on the master side only.

    I'll come back to you if anything is missing.

    Regards,

    Srikanth Vemula.