Other Parts Discussed in Thread: UCC28019
Hi TI partner,
I would like to know how to design a turn-on circuit for UCC28019's narrow Vcc hysteresis without standby power?
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Hi John,
Thanks for your feedback.
As you can see the UVLO on and off points are very close just 1 voltage.
The normal solution is generated from an auxiliary power supply, like Buck converter or Flyback converter.
But here is the thing, we want to design a cheaper circuit without using convert to turn on UCC28019.
Do you have any solution can share with us?
Thank you.
Hello Alex
You can place a startup resistor from the high voltage dc to the VDD pin of the UCC28019 and add a 15V protection zener from VDD to ground.The resistor should be sized to deliver about 3.5mA of operating current.
Regards
John
Hi John,
I have calculated the power loss about the bleeding resistance which would consume 0.81W when we operate at the low line ac input voltage which is 90 Voltage.
unfortunately, we also need to work at the high line as input, is 264V, which would let bleeding resistance consume up to 9 times low line ac input voltage and it almost reaches 7.2W that is a huge loss and also cause a heating issue.
So I want to ask you. Would you have any suggestion which is suitable for designing 700W power supply?
Our initial idea is to use CCM PFC and LLC converter for this kind of power supply's solution.
Do you have any recommendations you can share with us?
Thank you and best Regard.
Hi John,
Once LLC starts up then the startup resistor can be biased off.
I think this is a great idea but I just don't know how to achieve this idea.
I appreciate if you can provide this idea's circuit for me.
Thanks
Best Regard.
Hi Alex,
Calculate the resistor based on the requirement to supply the ICC pre start current (100uA nom) at your value of low line.
If you make this about 0.5mA it will charge up the VDD bias cap to the UVLO(ON) level (10.5V).
The data sheet shows the ICC operating current as 3.5mA.
So the cap on VDD has to supply this current for the startup time before VDD drops to UVLO(off)
This means C = I*T/(UVLO(on)-UVLO(off)) = 3.5*T
T is the start up time set by your LLC.
If the bias rail from the LCC reaches its set point before UVLO(off) is reached on the pfc then the system will startup without issue.
Regards
John
Hi John,
What I understand is the 3.5mA operating current which is at no gate load that means no operating Mosfet and not transferring power.
As you can see I use red mark to highlight the significant information, No Gate Load, at the below figure.
The working current I believe is at least 8mA. I also mark it as following green circle.
The point of the voltage which is UVLO(on) and UVLO(off) can decide the size of the capacitor.
Unforturenly, UVLO(on) minus UVLO(off) equal 1V.
If the output voltage raising time requires 50mS, let us turn back to the theory and write it down as below.
C = I*T/(UVLO(on)-UVLO(off)) = (8*10^-3)*(50*10^-3)/1=400uF
We need a huge auxiliary capacitor and it also impacts to the turn-on time.
The normal turn-on time is required 3 Sec.
If we set 0.5mA is our charging current, it would take 8.89Sec. I show the calculation graph as the red line at the below figure.
We need to change our design for 3 Sec turn-on requirement.
But the resistance should be very small as 54Komh. I show the calculation graph as the blue line at the below figure.
This resistance would take 0.645W at high line input voltage. (264^2)/(2*54000)=0.645(W)