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Power Up Problems with TPS65920

Howard Robson
Intellectual 415 points
Other Parts Discussed in Thread: TPS65920

I am in the prototype testing phase on a project using OMAP3530CBC and TPS65920.  We have 5 prototype boards, and with 2 of them we have problems with the power up sequence of the TPS65920.  In these cases we only get VIO powering up - VDD1 and VDD2 never power up.  We would like to resolve this problem before we revise the board.  Here is what we have:

  1. Layout done observing guidelines of application note.  Adequate trace thickness for power traces.
  2. VBAT = 3.3V (this application does not actually use a battery and is supplied by an external higher power 3.3V regulator that supplies all the boards in the system.

These I are my questions/observations:

  1. I have seen the note somewhere in the data sheet that mentions the "magical" 3.2V limit, but the data sheet contradicts itself as in other places there is mention of a lower voltage limit of 2.7V.  Is the limit 3.2V or 2.7V?  If the limit is 3.2V, I would contend that this is not optimal for wide applicability as 3.3V is probably the most common system voltage nowadays, and the TPS65920 should at least be compatible with the -5% tolerance limit of 3.3V (3.165V).
  2. On the 2 boards that do not power up correctly I have raised VBAT to > 4.0V and this does not change anything.

I have looked at all the posts that relate to this kind of problem and still cannot find a solution to the problem.

Any suggestions?

Thank you,

Howard Robson

  • 0
    TI__Genius 15100 points

    Hi Howard,

    Whenever power up problems were seen in the past there were two possible options - 32K oscillations werent correct or the layout did not allow for sufficient current. In your case it doesnt seem to be any of these. I am assuming the trace thickness are sufficient as you have specifically mentoned that. Can you tell how wide the traces are for VDD out and VDD in?

    Do you see any drop in the VBAT voltage at power-up?

    If you really do not see any problems with above observations then you can try to reflow the device and try again. There isnt any specific reason I can point for the two bad boards. Can you share your schematics with me, I can have a look at it. If three boards are functional then I am expecting your design is also fine and we are looking at board accuracy problems.

     

    For the 3.2V magical limit - I will update the data manual to specify what that is. Here is a quick explanation:

    There are multiple ways to power up the device - two of these being VBAT (battery) insertion, pressing PWRON switch (assuming this pad has aswitch mounted).

    Sometimes PWRON is directly connected to VBAT (specific user scenario). In this case the poweron event is the battery insertion event and this detects a threshold of VBAT>3.2V +/-100mV. Thats where the condition for 3.2V comes from. If you have a PWRON switch then this condition is not applicable (may require 3.2V +/=100mV at first powerup) because pressing the poweron switch and creating a negative edge acts as a power-on event. For this VBAT > 3.2V is fine.

    The 2.7V is actually the lower voltage threshold where the device will stay ON. Any lower voltage than 2.7V the device will power off. However, you cannot power-on the device for 2.7V<VBAT<3.2V condition. Think this as a hysterisis curve, if you may.

    I hope the battery level confusion is clear with the above explanation.

     

    Regards,

    Gandhar.