• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 63 subscribers
  • Views 581 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS56C215: Margin High - OVP issue

Julian Chen
Expert 2550 points
Part Number: TPS56C215

Dear E2E Member,

Our Customer use TPS56C215 and use MOS(Q8) to margin low.

But VFB will trigger OVP when margin low. (Margin high is normal)

I also suggest RD to use 10R(N5) at Gate of Q8 MOS, but no improve.

Did you have any suggestion for circuit or layout to improve this issue.

  • 0
    TI__Expert 8245 points
    Hi,

    Since the width of on-pulse is short (~200ns), it's hard to improve the issue due to the existance of parasitic capacitance between gate and source. Source voltage will unavoidably rises up when gate's up. May be you can try another MOSFET with smaller Qg or use a larger gate resistor. Also, you can try a smaller ramp of MARGIN_DN signal.