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LM5122: LM5122 - Is not synchronizing correctly. SYNC/RT Is not behaving as I would expect. I need a schematic or model of the input to optimize my circuit.

Bob Hewitt
Prodigy 80 points
Part Number: LM5122

I have a master slave arrangement to provide current sharing.  There are two frequencies to which synchronize: 500kHz and 392kHz.  These two frequencies are within the +40% to -20% range for synchronization.

The clock is generated by a 74ACT157DT with a 33.32 ohm series resistor in the output.  I have a 21.5K ohm RT resistor in parallel with a 3.3nF capacitor.  The reason for the capacitor is to eliminate the negative excursion from going below 0.3V.  With this arrangement, I have a board that is either skipping pulses or not supplying the a Freq/2 output.

I'd like to know if the 21.5K ohm RT resistor is correct to appropriately cover the frequency range.

The input load to the of the SYNC / RTinput must not be high impedance, but more complex input. It would be nice to get a spice / schematic for the SYNC/RT input, so that I can simulate the actual response so I can optimize it without a lot of experimentation.

I get the following response at the input to the SYNC/RT pin:

The Output from the SyncOut is either no clock, or a clock with skipped pulses:

  • 0
    TI__Mastermind 40080 points

    The expert for this part is on business trip and your post will be replied once he is back to office.

    And could you please share your schematic so that he can check it in more detail?

  • 0
    TI__Guru 58171 points
    Hi

    Please check the Table 1 in the datasheet. SYNCOUT is disabled in Slave1 & Master2 modes.
    Also, please make it sure your external clock is twice faster than switching frequency. Refer the section 7.3.11 in the datasheet.
    One more thing is the voltage at the RT pin. To be synchronized, RT pin voltage should go above 2.9V at rising edge and should drop down below 1.6V at falling edge. Refer OSCILLATOR section in the Electrical Characteristics table.

    Regards,
    EL
  • 0 in reply to EricLee
    Prodigy 80 points

    This circuit has been working as designed.  I believe we are seeing a corner case, where the low voltage may not be falling far enough below 1.6V.

    In my design I placed a 3.3nF capacitor in parallel with the 21.5K ohm resistor to increase the rise time.  This is done to reduce the jitter.

    CPP_TXV_LM5122_SyncOut_has_no_output.xlsx

  • 0 in reply to EricLee
    Prodigy 80 points

    Hi Eric,

    All those items are have been checked.  I added the schematic and the scope plots for the review.

    Also I want to make sure that the value of the RT resistor is correct to allow both a 500kHz and 392kHz sync signal to be used.

    Thank you,

    Bob

  • 0 in reply to EricLee
    Prodigy 80 points

    Hi Eric,

    When do expect to get the expert in to review the data that I sent.  This is a board that is in production and I need a answer fairly quickly so that I can get the rework instructions written and approved.

    Best Regards,

    Bob Hewitt

  • 0 in reply to Bob Hewitt
    TI__Mastermind 21720 points

    Hi Bob,

    Regarding the provided waveforms it looks like the frequency of the RT signal is only 250kHz. To SYNC the oscillator to 500kHz the SYNC frequency will need to be 1MHz when the LM5122 is in Master 1 mode. To synchronize the clock to 392kHz and 500kHz the input frequency is going to need to be 784kHz and 1MHz respectively. To be with in the +40/-20% range of clock synchronization it would be good to set the RT resistor to the switching frequency of 440kHz. This is an RT resistor value of about 20.4kOhm. Please try this and let me know if you have any questions.

    Thanks,

    Garrett

  • 0 in reply to Garrett Roecker
    Prodigy 80 points

    Hi Garret,

    The input clock to the LM5122 will be at two frequencies 500kHz and 394kHz. Since the design is a two phase design, the master and slave will be operating at 250kHz and 192kHz.  Since the master and slave are interleaved, the output harmonic content will still be 500kHz and 394kHz. Since this design is already in production, the RT resistor I have is 21.5k instead of 20.4kHz. This is within 5% of your value, I'd like to know that there is still enough margin in the 21.5K value to not have any issues.

    In the attached excel file, the failing Clock input with the (21.5K / 3.3nF - Blue waveform) circuit was done to provide a crisp rising edge to reduce jitter in the signal. My observation of this waveform (in hindsight) is that the falling edge of the waveform might be marginal with respect to the 1.6V lower threshold when we run this over temperature (45 degC to 5 degC). As you can see, the falling edge drops to about 1V but rises to about 1.25V before driving 6V. I want to here your thoughts on why this waveform fails to provide a slave clock.

    Changing the capacitor from 3.3nF to 22pF has changed the input clock waveform significantly and I think it better meets the input requirement for the input clock. The rising edge is steeper through 3.6V and then does not exceed 5V.  On the falling edge, it gets to 1.4V and then continues to drop to 0.6V.  I'd like you to comment of the reliability of this clock waveform to meet the input clock requirements.

     

  • 0 in reply to Bob Hewitt
    Prodigy 80 points
    I am waiting for a reply to my last post.
  • 0 in reply to Bob Hewitt
    TI__Guru* 78060 points
    Hi Bob,

    I read you post and it seems your RT resistor is not correctly chosen. The datasheet section 7.3.11 on page 26 says:

    "With the configuration in Figure 23, the frequency of the external synchronization pulse is recommended to be within +40% and –20% of the internal oscillator frequency programmed by the RT resistor. For example, 900-kHz external synchronization clock and 20-kΩ RT resistor are required for 450-kHz switching in master1 mode."

    From your Jul 6 post, it seems you just want to switch each phase at about 250kHz or 198kHz. According to above datasheet paragraph, your RT resistor should be at about 40k instead of your 21.5k. The 40k sets a standalone operation frequency at 225kHz, which is +13% higher than 198kHz, and -11% lower than 250kHz. When you apply either 500kHz or 398kHz, the intended switching frequency for each phase is 250kHz or 198kHz, and it falls within the required +40% and -20% of the native switching frequency (225kHz) programmed by the 40k RT resistor. However, when you use 21.5k in your product, you make the external clock outside this +40% and -20% range.


    Thanks,
    Youhao