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UCC28951-Q1: Sync operation for external clock

Hidekazu Someno
Expert 5130 points
Part Number: UCC28951-Q1
Other Parts Discussed in Thread: UCC28950

Hello Team,

Please tell me about the following two items for UCC28951-Q1 used as SLAVE mode with external clock.

According to SLUS609 application note written for UCC28950, family device in the same application; 

1.  The pulse width of external  clock signal to Sync-pin has been needed as >300ns.

     Is this 300ns _min applied to both logic "high" and "low "regardless of frequency for UCC28951-Q1?

2. External clock to SYNC pin should need the frequency over x1.8  of internal frequency set by RT resister.

   If internal frequency has +/-15kHz variation as 100kHz_typ,   How is estimated the minimum frequency of external clock?

   Is 207kHz(=115kHz*1.8)  needed as minimum frequency?   or  is 180kHz(100kHz_typ*1.8) is enough?

Best regards,

Hidekazu Someno

  • 0
    TI__Mastermind 25570 points
    Hello Someno-san

    I will add these issues to the other open SYNC signal issues we discussed via email - I hope to have answers for you by Monday

    Regards
    Colin
  • 0 in reply to Colin Gillmor
    TI__Expert 5130 points

    Colin-san,

    How about this question?

    I couldn't find any comments about this question in your explanation to SYNC signal in your email.

    Best regards,

    Hidekazu Someno

  • 0 in reply to Hidekazu Someno
    TI__Mastermind 25570 points
    Hello Someno-san

    1/ The positive going pulse width should be > 300ns. The minimum negative going pulse width should be similar - but I have not confirmed this on the bench - I will try to do this on Monday. Normally the SYNC signal would be 50% duty cycle - or 5uS for a 100kHz syncronised frequency. These times would be independent of frequency.

    2/ The sync frequency must be 1.8 times greater than the free running frequency of the controller. 207 kHz in your example.. Actually what would happen is that the designer would choose the SYNC frequency first and then set the free running frequency to meet the 1.8 times condition.

    Regards
    Colin
  • 0 in reply to Colin Gillmor
    TI__Mastermind 25570 points

    Hello Someno-san

    I checked a UCC28950 device on the bench this morning and both the positive going and negative going pulses should have a pulse width > 300ns.

    All frequencies mentioned are those at the OUTx pins.

    Please note that there is a lot of margin on these pulse widths. I got a UCC28950 set to a free running frequency of 100kHz to synchronise over the range 15kHz to 1MHzz using a 20ns wide negative going pulse. The controller needed a minimum 100ns positive going pulse and it synchronised from 75kHz to 1MHzkHz

    The controller did synchronise up to 1MHz at 50% duty cycle where Ton = Toff = 250ns.  NOTE: The dead times become a significant proportion of the switching period at such high frequencies and the duty cycle available to the power converter stage is therefore limited.

    My input signal was 0/5V

    Regards
    Colin