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TPS65920: Questions on CLKREQ, NRESWARM and NRESPWRON, Master and Boot

Other Parts Discussed in Thread: TPS65920, OMAP3503, TPS65950

Customers questions:

Q1: What is the difference in PWRON functionality in these two modes? It seems like in slave mode PWRON actually turn on/off the PMIC and in Master Mode, PWRON just resets the system....
A1: master and slave really depends on the system architecture. If you are using OMAP+PMIC only then you should use master mode. For slave mode you need another master PMIC that will turn ON the slave PMIC.

Q2: I have seen some documentation that has nRESWARM connected to a reset push-button, others connect the reset push-button to the nRESPWRON pin...Can you expand bit more on nRESWARM going into the TPS65920? Can it be used as a system reset? What is the difference between nRESPWRON and nRESWARM?
A2: nRESWARM is an input to TPS65920, it is used as a soft reset for the device. This reset signal is tied to OMAP so OMAP can control the soft reset to TPS65920. To use this as a warmreset you will have to program the internal memory of TPS65920 with the appropriate sequence. You can find a sample sequence in the TRM.
nRESPWRON is an output signal from TPS65920 that takes OMAP out of reset after the initial power-up of TPS65920.

Q3: CLKREQ - I have seen documentation connecting this pin to the SYS_CLKREQ on the OMAP. The Beagle Board connects this pin directly to VIO (1.8V) I wonder if this is done to speed up the power-on sequence so that the PMIC doesn't have to wait for a request from the Processor, but instead the PMIC starts providing the HFCLK as soon as VIO becomes stable....any comments?
A3: No, CLKREQ connection has nothing to do with speed of power-up sequnce. There are two control signals on TPS65920 - nSLEEP1 and CLKREQ. You can control the power resources in the device by toggling these signals and having the correct sequences (Active to Sleep and Sleep to Active) in the device memory.

  • Hi, I'm using OMAP3503 and TPS65950.

    I would like to implement a kind of cold reset via a switch button to do a power on reset (reset to OMAP hardwarely) in addition to the wram reset

    Must i connect this external hardware reset to the "SYS_nRESPWRON" pin of OMAP?

    Talking about debouncin time of TPS65950 on PWRON pin, how to determine the R/C values to respect the timing?

    Could any one provide me the schematic for PWRON and cold reset?

    regards

    MIK

  • Hi,

    Connecting reset for sys_nrespowron on OMAP will only reset the OMAP device. Nothing will affect the PMIC. This will not really serve the purpose of a cold reset where you should (or want to) reset the whole platform. 

    We recommend that you use a software reset on this platform as many others use. There are no issues with this system and I dont think have access to external cold reset circuitry is really going to help or make any or lot of difference.

    I dont understand your question about PWRON debounce. This debounce is default based on the device and not on any external RC values.

     

  • Hi,

    Thanks for your reply. In the OMAP TRM section 4.5.8, we could perform the cold reset via sys_nrespwron. That 's what we want to do.

    So what is the minimum timing of this reset ? i didnt find reset timing information any where in the supports documents!

    In any way, we will construct an external warm reset (warm rest push button) to be safe?

    regards

    M.MIK  

  • You may want to check the minimum timing requirement for OMAP in the OMAP datasheet or ask your OMAP contact. I dont have that information.