LP8860-Q1: EMI issue

Hello Dongbao,

Thank you for promoting LP8860-Q1 and reaching out.

There could be some limitations about how much you could improve EMI but the following (below) are some considerations that have been successfully implemented in the past and helped to reduce EMI levels to acceptable levels:

1. Gate resistor, BOOST_DRIVER_SIZE[1:0], and FET selection. These are the three first things I would consider:

(i) From the schematic it seems that you are using the 10ohm gate resistor (for boost FET). That value is the general recommendation but some customers have successfully been able to use slightly higher values without penalty on the performance (as it would be expected if you went to the other extreme and increased it too high). If a slightly higher FET resistor is acceptable (not high losses) that could help improve EMI performance. This level of evaluation is usually done by the customer and it could greatly help.
Has your customer explored this option?

(ii) Another options that could be used (isolated or in conjunction with the above consideration) is to select the min Max gate current sink/source by selecting the lowest possible value of BOOST_DRIVER_SIZE=00 register. This has also been successfully implemented in the past by some customers and helped them meet EMI requirements justifying some sacrifice on the efficiency.
Has your customer explored this option?
Decision should be based on gate charge (of the NFET) considerations (based on bench measurements).
From your EEPROM settings it seems that you are using the highest BOOST_DRIVER_SIZE settings.

(iii) Potentially selecting a FET with relatively higher gate capacitance and package with better inductance could help as well. I understand there will be limitations with this.

 Find a summary below about these three points (the first two ones are important).

2. PCB layout:
In addition to the above of course PCB layout could play a role. Although assuming the customer has followed a good PCB layout practice and/or EMI requirements are too stringent the return value of re-optimizing the PCB may need to be re-evaluated since a fairly decent PCB layout often doesn’t render the expected EMI performance by just re- tweaking it. Has the PCB layout been reviewed to ensure good loop and EMI considerations?

3. EMI mitigation/reduction circuitry:
What other additional circuitry has been considered to improve EMI?
Please refer to the following link for more details
www.ti.com/.../snva813.pdf

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SUMMARY OF POINT 1 ABOVE:
1. Ringing on the gate voltage could be improved by:
(a) Increasing value of gate resistor (some customers have successfully tried higher than 10mohm without sacrificing performance and getting a good EMI improvement in return).
(b) Selecting the minimum Max gate current sink/source (0.4/0.45A) defined by BOOST_DRIVER_SIZE=00
(c) Selecting a FET with relatively higher gate capacitance and package with better parasitic (L).
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Now, in terms of passive selection (CIN and COUT): the right choice would obviously depend on your settings, conditions, and requirements. The datasheet provides some general recommendations and there could be some flexibility depending mainly upon your specific conditions/requirements. For example depending on the quality of your input signal you could relax a little bit CIN. The optimum value of COUTwould depend on acceptable VOUT ripple values and stability considerations. Often it is more challenging to be able to relax COUT than CIN but, ultimately stability measurements and ripple measurements using your conditions would determine whether you could safely deviate COUT from the datasheet general recommendations.

I hope that helped.

Kind Regards,

David