• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 62 subscribers
  • Views 368 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

UCC2895: BLOCK DIAGRAM QUESTION

Rossano Valsecchi
Prodigy 240 points
Part Number: UCC2895


Hello

I can't understand the minimun duty cycle adjustement of UCC2895.

If the EAOUT pin is fixed below 0.8V,  looking at the block diagram it seems that the PWM comparator stops oscillating.

Reading the data I see that with EAOUT = 650mV the duty cycle may vary from 0% to 1.4%. 

I need to evaluate the voltage at EAOUT that will produce the minimum duty cycle and the maximum duty cycle with the best linearity achievable.

Thank you

Rossano

  • 0
    TI__Mastermind 25570 points
    Hello Rossano

    The datasheet shows a 800mV offset from RAMP to the PWM comparator.
    I think that the 'Minimum Phase Shift' specification is really just setting an upper bound on the duty cycle (1.4%) when EAOUT = 650mV. Further - the no-load comparator may or may not be active when EAOUT is in this region - it will vary from device to device.

    You can expect that the plot of EAOUT versus Duty cycle would be linear but the slope and offset of the graph will vary a little from device to device. A linear plot means that control loop does not have to deal with second order effects in the Voltage to Duty cycle transfer function.

    The feedback loop will always drive EAOUT to whatever voltage is necessary to achieve the required duty cycle, and this voltage will vary a little from device to device.

    Regards
    Colin