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BQ25890: Expected behaviour at end of charge / full charge

Part Number: BQ25890

Hi there,

I have a design that uses a BQ25890 to charge a single lithium cell in a battery pack. The BQ25890 is configured over I2C by a microcontroller, running software that I have written. I'm a little worried that I'm doing something wrong and not charging the battery to completion, because the pack can also be inserted into an (Android-based) phone, also using a BQ25890, and the developer that configured the linux driver was originally able to charge the battery further. It seems he's struggling to reproduce the linux device tree config he had, so I thought it would be good to make sure I've got my end right.

The charger is configured with VREG = 4.208V (the default). I've also set the termination current limit (ITERM) to 64mA. This isn't over USB, so all the power handshake logic is disabled, and we set INLIM manually.

I can charge a battery with a multimeter probe connected across the actual battery terminals and the charging current supplied by a bench supply. I see the usual constant-current charge, with occasional pauses due to thermal limiting (good!). Then I start to see the current tail off as we enter the constant voltage region. Confusingly, the voltage across the battery terminals in that region is about 4.05V. Should I expect that, or does the fact this is 150mV under VREG suggest that something is wrong? (I don't think it's a hardware problem: the BAT_1 and BAT_2 terminals of the charger IC are connected directly to one terminal of the battery, and the other terminal is connected to the same ground as the charger IC).

After the battery has been CV charging for a while, I start to see short pulses (maybe one second?) of high current (1A or so at the bench supply), with the voltage across the terminals going up to about 4.25V (this number is pretty approximate - I'm not sure whether the multimeter is stabilising in time).

When the charge cycle finishes, the cell has a voltage of about 4.05V (as you'd expect). After a weekend disconnected (so the state of charge shouldn't have changed significantly), the voltage has dropped to 3.965V. This seems reasonable, I think?

Does this description sound like the correct behaviour to charge a 4.2V cell? If not, could you tell me which numbers look suspect and I'll look harder at how I'm configuring them on the charger.

Many thanks,

Rupert

  • The charger regulates the BAT pin voltage of the IC, but not the battery pack terminal. To charge the battery pack as much as possible, resistance compensation (IRCOMP) is recommended. Please refer to p25 of the d/s for the details. And it is normal that the battery voltage drops a little bit after the charge is terminated, i.e. battery relaxation. Thanks!

     

  • Hi,

    Thank you for the reply, but I don't think it answers my question. I understand that IRCOMP would make a difference when fast-charging (constant current mode), but it surely won't make any difference when the battery is almost full - there's very little current going in to the battery. Also, yes, I expected battery relaxation. I gave voltages before and after relaxation to avoid just giving a bare voltage without explaining when it was measured.

    I think my question boils down to:

    1. What voltage should I see across the battery terminals when charging is almost complete, as a function of VREG?
    2. How does that voltage relate to the higher voltage seen in the short high-current pulses when the battery is almost charged?

    Thanks!

    Rupert

  • 1. The BAT pin voltage will be very close to VREG (e.g. 4.208V) when charging is almost complete.

    2. I do not observe high current pulses in CV mode described by you. Please provide more details to duplicate the behavior and related waveforms.

    I do observe current pulses after the charge is terminated. Referring to page 21 of the d/s, In order to improve light-load efficiency, the device switches to PFM control at light load when battery is below minimum system voltage setting or charging is disabled. During the PFM operation, the switching duty cycle is set by the ratio of SYS and VBUS.

    Thanks!

  • Hi there,

    Thank you very much for the response. I think the VREG issue was a misconfiguration error at our end - I updated the EEPROM contents that determine how we write to the charger and I see a VBAT of 4.2V as expected. Frustratingly, I can't reproduce what we were seeing beforehand, but hopefully the microcontroller was just writing a silly value of VREG.

    For the second behaviour (high current pulses), I had mis-diagnosed what was going on. We have made it as far as CV mode, but near the start. The current going in to the battery when we stop is >1A. I don't understand why the charge is stopping, but I'll post a fresh question with details in a minute.

    Rupert
  • Thank you very much for the update. It's great that all issues are resolved.